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參數(shù)資料
| 型號(hào)： | C9851BT |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | TSSOP-48 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 131K |
| 代理商： | C9851BT |
+/+
…when timing is critical
C9851
Clock Generator for Pentium
III Server and Workstation Applications
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
1.0
2/1/2000
MILPITAS, CA TEL 408-263-6300, FAX 408-263-6571
Page 1 of 13
http://www.imicorp.com
Product Features
Six pairs of current referenced differential clocks
Two 3V 180
° displaced Mref clocks for DRCG
One 66.6 MHz reference output
One 14.318 MHz reference output
Select logic for Differential Swing Control, Test
mode, Hi-Z, Power-down, Spread spectrum, and
limited frequency select
IMI Spread Spectrum for EMI reduction
48 Pin SSOP Package
Product Description
This device provides the necessary clocks for a
differential host bus system in multi-processor servers
and workstations.
It also generates a 66.6MHz hub
clock for interfacing with a complimentary part, the IMI
B9852. The 2 Mref clock outputs are 180 degrees out
of phase and are used for interfacing with the Direct
Rambus Clock Generator (DRCG), IMI C9820, C9821,
or C9822.
This device integrates the IMI spread
spectrum technology for optimum EMI reduction.
Frequency Selection Table
SEL 100/133
SELA
SELB
CPU(1:6), CPU#(1:6)
3VMref,
3Vmref_b
3V66
REF
0
100 MHz
50 MHz
66.67 MHz
14.318 MHz
0
1
100 MHz
Low
0
1
0
200 MHz
50 MHz
66.67 MHz
14.318 MHz
0
1
Hi-Z
1
0
133.3 MHz
66.67 MHz
14.318 MHz
1
0
1
25 MHz
50 MHz
66.67 MHz
14.318 MHz
1
0
200 MHz
66.7 MHz
66.67 MHz
14.318 MHz
1
REF/2
REF/4
REF
Block Diagram
Table 1
Pin Configuration
VSSR
Ref
VDDR
XIN
XOUT
VSSR
VDDM
3VMref
3VMref_b
VSSM
VDD
VSS
VDDL
3V66
VSSL
SEL100/133
MultSel0
MultSel1
VDD
VSS
SelA
SelB
Spread#
PwrDwn#
VDDR
VSS
VDDC
CPU1
CPU1#
VSSC
CPU2
CPU2#
VDDC
CPU3
CPU3#
VSSC
CPU4
CPU4#
VDDC
CPU5
CPU5#
VSSC
CPU6
CPU6#
VDDC
I_Ref
VSSI
VDDI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
OSC
VCO
I
Control
VDDI
I_Ref
VSSI
VDDR
VSSR
REF
CPU (1:6)
CPU (1:6)#
VDDM
3VMRef
3VMRef_b
VSSM
VDDL
3V66
VSSL
Spread#
SelB
SEL100/133
XOUT
XIN
MultSel(0:1)
PwrDwn#
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