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參數(shù)資料
| 型號： | C9851 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Clock Generator for Pentium III Server and Workstation Applications |
| 中文描述： | 時鐘奔騰III服務(wù)器和工作站發(fā)電機(jī)應(yīng)用 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大小： | 122K |
| 代理商： | C9851 |
Clock Generator for Pentium
III Server and Workstation Applications
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07068 Rev. **
05/04/2001
Page 1 of 14
PRELIMINARY
C9851
Product Features
Six pairs of current referenced differential clocks
Two 3V 180
°
displaced Mref clocks for DRCG
One 66.6 MHz reference output
One 14.318 MHz reference output
Select logic for Differential Swing Control, Test
mode, Hi-Z, Power-down, Spread spectrum, and
limited frequency select
Cypress Spread Spectrum for EMI reduction
48 Pin SSOP Package
Product Description
This device provides the necessary clocks for a
differential host bus system in multi-processor servers
and workstations. It also generates a 66.6MHz hub
clock for interfacing with a complimentary part, the
Cypress B9852. The 2 Mref clock outputs are 180
degrees out of phase and are used for interfacing with
the Direct Rambus Clock Generator (DRCG), C9820,
C9821, or C9822. This device integrates the Cypress
spread spectrum technology for optimum EMI
reduction.
Frequency Selection Table
SEL 100/133
SELA
SELB
CPU(1:6), CPU#(1:6)
3VMref,
3Vmref_b
50 MHz
Low
50 MHz
Hi-Z
66.67 MHz
50 MHz
66.7 MHz
REF/4
Table 1
3V66
REF
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
100 MHz
100 MHz
200 MHz
Hi-Z
133.3 MHz
25 MHz
200 MHz
REF/2
66.67 MHz
Low
66.67 MHz
Hi-Z
66.67 MHz
66.67 MHz
66.67 MHz
REF
14.318 MHz
Low
14.318 MHz
Hi-Z
14.318 MHz
14.318 MHz
14.318 MHz
REF
Block Diagram
Pin Configuration
VSSR
Ref
VDDR
XIN
XOUT
VSSR
VDDM
3VMref
3VMref_b
VSSM
VDD
VSS
VDDL
3V66
VSSL
SEL100/133
MultSel0
MultSel1
VDDA
VSSA
SelA
SelB
Spread#
PwrDwn#
VDD
VSS
VDDC
CPU1
CPU1#
VSSC
CPU2
CPU2#
VDDC
CPU3
CPU3#
VSSC
CPU4
CPU4#
VDDC
CPU5
CPU5#
VSSC
CPU6
CPU6#
VDDC
I_Ref
VSSA
VDDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
OSC
VCO
I
Control
VDDA
I_Ref
VSSI
VDDR
VSSR
REF
CPU (1:6)
CPU (1:6)#
VDDM
3VMRef
3VMRef_b
VSSM
VDDL
3V66
VSSL
Spread#
SelA
SelB
SEL100/133
XOUT
XIN
MultSel(0:1)
PwrDwn#
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