參數(shù)資料
型號: C8051F982-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 2/4頁
文件大小: 0K
描述: IC MCU 8BIT 4KB FLASH 20QFN
產(chǎn)品培訓模塊: C8051F9xx Lower Power MCUs
Serial Communication Overview
視頻文件: Designing for Low Power Operation
特色產(chǎn)品: C8051F91x/0x MCU Series Development Kit
C8051F98x and C8051F99x Low-Power MCU’s
標準包裝: 122
系列: C8051F9xx
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SMBus(2 線/I²C),SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 4KB(4K x 8)
程序存儲器類型: 閃存
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 10x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-UFQFN 裸露焊盤
包裝: 管件
其它名稱: 336-1949-5
400 West Cesar Chavez, Austin, TX 78701 www.silabs.com
Errata Details
1.
Capacitive Sense Pin Monitor
Description: An issue has been identified with the capacitive sense pin monitor function when the device
enters Suspend mode. If the pin monitor is enabled, under some circumstances, conversions may be
continuously initiated.
Impacts: The Capacitive sense conversion may not complete due to continuously being restarted.
Workaround: Disable all pin monitor functionality (CS0PM = 0x00) before entering Suspend mode.
Resolution: Fixed in Rev B and later.
2.
CS0MD1 Bit Mapping
Description: Bit 4 and Bit 5 of CS0MD1 have been incorrectly mapped to Bit 5 and Bit 6.
Impacts: Both the CS0 Digital Polarity Select and the CS0 Double Reset Select function share the same bit
(Bit 5) in the CS0MD1 register. This may cause a limitation in functionality if these functions are being used.
Workaround: Since making a change to one of the functions will cause a change to the other function, care
should be taken when setting up either function. If Bit 5 and Bit 6 are not written, then the device will follow
the default behavior described in the data sheet.
Resolution: Fixed in Rev B and later.
3.
No ADC Input on P1.4
Description: An issue has been identified that prevents P1.4 from being routed to the ADC.
Impacts: On C8051F996/7/8/9 devices, P1.4 cannot be used as an analog input for the ADC. This behavior
does not affect C8051F990/1/2/3/4/5 devices.
Resolution: Fixed in Rev B and later.
4.
SmaRTClock Startup Time
Description: A modification was made to the SmaRTClock crystal driver circuit.
Impacts: The startup time of the SmaRTClock crystal oscillator is longer than other devices in the ‘F9xx
family. Instability may occur at voltages above 3.0 V. The “Oscillator Robustness Test” described in the data
sheet is not a valid way to determine oscillator robustness for this silicon revision.
Workaround: Disable automatic gain control or use bias doubling to increase the drive current if the crystal
has high ESR (> 40 k
) or if the supply voltage is greater than 3.0 V.
Resolution: Fixed in Rev B and later.
5.
Non Sleep Mode Current
Description: An internal pull-up transistor is enabled, drawing approximately 100 A, when the precision
oscillator is disabled.
Impacts: In all power modes other than Sleep mode, device power consumption will be 100 A higher than
data sheet specifications if the precision oscillator is disabled.
Resolution: Fixed in Rev B and later.
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