
C8051F80x-83x
50
Rev. 1.0
SFR Address = 0xBC
SFR Definition 8.1. ADC0CF: ADC0 Configuration
Bit
76543210
Name
AD0SC[4:0]
AD0LJST
AD08BE
AMP0GN0
Type
R/W
Reset
11111001
Bit
Name
Function
7:3
AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock
requirements are given in the ADC specification table.
2AD0LJST
ADC0 Left Justify Select.
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.
Note: The AD0LJST bit is only valid for 10-bit mode (AD08BE = 0).
1AD08BE
8-Bit Mode Enable.
0: ADC operates in 10-bit mode (normal).
1: ADC operates in 8-bit mode.
Note: When AD08BE is set to 1, the AD0LJST bit is ignored.
0AMP0GN0
ADC Gain Control Bit.
0: Gain = 0.5
1: Gain = 1
AD0SC
SYSCLK
CLK
SAR
-----------------------1
–
=