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參數(shù)資料
| 型號(hào)： | C8051F533A-IM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 11/220頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC 8051 MCU 4K FLASH 20QFN |
| 產(chǎn)品培訓(xùn)模塊： | Serial Communication Overview |
| 標(biāo)準(zhǔn)包裝： | 91 |
| 系列： | C8051F53x |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 25MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，POR，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 16 |
| 程序存儲(chǔ)器容量： | 4KB（4K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 20-VFQFN 裸露焊盤(pán) |
| 包裝： | 管件 |
| 配用： | 336-1488-ND - KIT DEV C8051F53XA, C8051F52XA 336-1457-ND - ADAPTER PROG TOOLSTICK F530TPP 336-1456-ND - ADAPTER PROG TOOLSTICK F530MPP |
| 其它名稱： | 336-1497-5 |
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C8051F52x/F53x
108
Rev. 1.4
11.2. Power-Fail Reset / VDD Monitors (VDDMON0 and VDDMON1)
C8051F52x-C/F53x-C devices include two VDD monitors: a standard VDD monitor (VDDMON0) and a
level-sensitive VDD monitor (VDDMON1). VDDMON0 is primarily intended for setting a higher threshold to
allow safe erase or write of Flash memory from firmware. VDDMON1 is used to hold the device in a reset
state during power-up and brownout conditions.
Note:
VDDMON1 is not present in older silicon revisions A and B. Please refer to Section “20.4. VDD Monitors and
VDD Ramp Time” on page 211 for more details.
When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply
monitors (VDDMON0 and VDDMON1) will drive the RST pin low and hold the CIP-51 in a reset state (see
Figure 11.2). When VDD returns to a level above VRST, the CIP-51 will be released from the reset state.
Note that even though internal data memory contents are not altered by the power-fail reset, it is impossi-
ble to determine if VDD dropped below the level required for data retention. If the PORSF flag reads 1, the
data may no longer be valid.
VDDMON0 is enabled and is selected as a reset source after power-on resets; however its defined state
(enabled/disabled) is not altered by any other reset source. For example, if VDDMON0 is disabled by soft-
ware, and a software reset is performed, VDDMON0 will still be disabled after that reset.
VDDMON1 is enabled and is selected as a reset source after power-on reset and any other type of reset.
There is no register setting that can disable this level-sensitive VDD monitor as a reset source.
To protect the integrity of Flash contents, the VDD monitor (VDDMON0) must be enabled to the
higher setting (VDMLVL = '1') and selected as a reset source if software contains routines which
erase or write Flash memory. If the VDD monitor is not enabled and set to the higher setting, any
erase or write performed on Flash memory will cause a Flash Error device reset.
Note:
Please refer to Section “20.5. VDD Monitor (VDDMON0) High Threshold Setting” on page 212 for important
notes related to the VDD Monitor high threshold setting in older silicon revisions A and B.
The VDD monitor (VDDMON0) must be enabled before it is selected as a reset source. Selecting the
VDDMON0 as a reset source before it is enabled and stabilized may cause a system reset. The procedure
for re-enabling the VDD monitor and configuring the VDD monitor as a reset source is shown below:
1. Enable the VDD monitor (VDMEN bit in VDDMON = 1).
2. Wait for the VDD monitor to stabilize (see Table 2.8 on page 32 for the VDD Monitor turn-on time). Note:
This delay should be omitted if software contains routines which write or erase Flash memory.
3. Select the VDD monitor as a reset source (PORSF bit in RSTSRC = 1).
See Figure 11.2 for VDD monitor timing; note that the reset delay is not incurred after a VDD monitor reset.
Note:
Software should take care not to inadvertently disable the VDD Monitor (VDDMON0) as a reset
source when writing to RSTSRC to enable other reset sources or to trigger a software reset. All
writes to RSTSRC should explicitly set PORSF to '1' to keep the VDD Monitor enabled as a reset
source.
11.2.1. VDD Monitor Thresholds and Minimum VDD
The minimum operating digital supply voltage (VDD) is specified as 2.0 V in Table 2.2 on page 26. The volt-
age at which the MCU is released from reset (VRST) can be as low as 1.65 V based on the VDD Monitor
thresholds that are specified in Table 2.8 on page 32. This could allow code execution during the power-up
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| C8051F533A-IMR | 功能描述:8位微控制器 -MCU 25 MIPS 4 kB 256 SPI UART LIN RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| C8051F533A-IT | 功能描述:8位微控制器 -MCU 4KB 12ADC 125C MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| C8051F533A-ITR | 功能描述:8位微控制器 -MCU 25 MIPS 4 kB 256 SPI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| C8051F533-C-IM | 制造商:Silicon Laboratories Inc 功能描述:25 MIPS, 4 KB, 256, SPI, UART, LIN 2.1, QFN20 - Rail/Tube 制造商:Silicon Laboratories Inc 功能描述:IC MCU 8051 4KB FLASH 20QFN |
| C8051F533-C-IMR | 制造商:Silicon Laboratories Inc 功能描述:25 MIPS, 4 KB, 256, SPI, UART, LIN 2.1, QFN20 - Tape and Reel 制造商:Silicon Laboratories Inc 功能描述:IC MCU 8051 4KB FLASH 20QFN |
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