- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗11114 > C8051F349-GM (Silicon Laboratories Inc)IC 8051 MCU 32K FLASH MEM 32-QFN PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | C8051F349-GM |
| 寤犲晢锛� | Silicon Laboratories Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 5/276闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC 8051 MCU 32K FLASH MEM 32-QFN |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Serial Communication Overview |
| 妯欐簴鍖呰锛� | 73 |
| 绯诲垪锛� | C8051F34x |
| 鏍稿績铏曠悊鍣細 | 8051 |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 25MHz |
| 閫ｉ€氭€э細 | SMBus锛�2 绶�/I²C锛�锛孲PI锛孶ART/USART锛孶SB |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯/寰�(f霉)浣嶏紝POR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 25 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 32KB锛�32K x 8锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 2.25K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2.7 V ~ 3.6 V |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 32-VFQFN 瑁搁湶鐒婄洡 |
| 鍖呰锛� | 绠′欢 |
| 閰嶇敤锛� | 336-1748-ND - ADAPTER TOOLSTICK FOR C8051F34X |
| 鍏跺畠鍚嶇ū锛� | 336-1349-5 |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�鐣�(d膩ng)鍓嶇5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�绗�110闋�绗�111闋�绗�112闋�绗�113闋�绗�114闋�绗�115闋�绗�116闋�绗�117闋�绗�118闋�绗�119闋�绗�120闋�绗�121闋�绗�122闋�绗�123闋�绗�124闋�绗�125闋�绗�126闋�绗�127闋�绗�128闋�绗�129闋�绗�130闋�绗�131闋�绗�132闋�绗�133闋�绗�134闋�绗�135闋�绗�136闋�绗�137闋�绗�138闋�绗�139闋�绗�140闋�绗�141闋�绗�142闋�绗�143闋�绗�144闋�绗�145闋�绗�146闋�绗�147闋�绗�148闋�绗�149闋�绗�150闋�绗�151闋�绗�152闋�绗�153闋�绗�154闋�绗�155闋�绗�156闋�绗�157闋�绗�158闋�绗�159闋�绗�160闋�绗�161闋�绗�162闋�绗�163闋�绗�164闋�绗�165闋�绗�166闋�绗�167闋�绗�168闋�绗�169闋�绗�170闋�绗�171闋�绗�172闋�绗�173闋�绗�174闋�绗�175闋�绗�176闋�绗�177闋�绗�178闋�绗�179闋�绗�180闋�绗�181闋�绗�182闋�绗�183闋�绗�184闋�绗�185闋�绗�186闋�绗�187闋�绗�188闋�绗�189闋�绗�190闋�绗�191闋�绗�192闋�绗�193闋�绗�194闋�绗�195闋�绗�196闋�绗�197闋�绗�198闋�绗�199闋�绗�200闋�绗�201闋�绗�202闋�绗�203闋�绗�204闋�绗�205闋�绗�206闋�绗�207闋�绗�208闋�绗�209闋�绗�210闋�绗�211闋�绗�212闋�绗�213闋�绗�214闋�绗�215闋�绗�216闋�绗�217闋�绗�218闋�绗�219闋�绗�220闋�绗�221闋�绗�222闋�绗�223闋�绗�224闋�绗�225闋�绗�226闋�绗�227闋�绗�228闋�绗�229闋�绗�230闋�绗�231闋�绗�232闋�绗�233闋�绗�234闋�绗�235闋�绗�236闋�绗�237闋�绗�238闋�绗�239闋�绗�240闋�绗�241闋�绗�242闋�绗�243闋�绗�244闋�绗�245闋�绗�246闋�绗�247闋�绗�248闋�绗�249闋�绗�250闋�绗�251闋�绗�252闋�绗�253闋�绗�254闋�绗�255闋�绗�256闋�绗�257闋�绗�258闋�绗�259闋�绗�260闋�绗�261闋�绗�262闋�绗�263闋�绗�264闋�绗�265闋�绗�266闋�绗�267闋�绗�268闋�绗�269闋�绗�270闋�绗�271闋�绗�272闋�绗�273闋�绗�274闋�绗�275闋�绗�276闋�
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
102
Rev. 1.3
11.2. Power-Fail Reset / VDD Monitor
When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 11.2). When VDD returns
to a level above VRST, the CIP-51 will be released from the reset state. Note that even though internal data
memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped below
the level required for data retention. If the PORSF flag reads 鈥�1鈥�, the data may no longer be valid. The VDD
monitor is enabled after power-on resets; however its defined state (enabled/disabled) is not altered by any
other reset source. For example, if the VDD monitor is enabled and a software reset is performed, the VDD
monitor will still be enabled after the reset. It is strongly recommended that the VDD monitor be left enabled
at all times for any system that contains code to write to Flash memory.
Important Note: The VDD monitor must be enabled before it is selected as a reset source. Selecting the
VDD monitor as a reset source before it is enabled and stabilized may cause a system reset. In applica-
tions where this reset is undesirable, a delay can be implemented between enabling the VDD monitor and
selecting it as a reset source. The procedure for configuring the VDD monitor as a reset source is shown
below:
Step 1. Enable the VDD monitor (VDM0CN.7 = 鈥�1鈥�).
Step 2. If desired, wait for the VDD monitor to stabilize (see Table 11.1 for the VDD Monitor turn-on
time).
Step 3. Select the VDD monitor as a reset source (RSTSRC.1 = 鈥�1鈥�).
See Figure 11.2 for VDD monitor timing. See Table 11.1 for complete electrical characteristics of the VDD
monitor.
SFR Definition 11.1. VDM0CN: VDD Monitor Control
Bit7:
VDMEN: VDD Monitor Enable.
This bit turns the VDD monitor circuit on/off. The VDD Monitor cannot generate system resets
until it is also selected as a reset source in register RSTSRC (SFR Definition 11.2). The VDD
Monitor must be allowed to stabilize before it is selected as a reset source. Selecting the
VDD monitor as a reset source before it has stabilized will generate a system reset.
lowing all POR resets.
0: VDD Monitor Disabled.
1: VDD Monitor Enabled.
Bit6:
VDDSTAT: VDD Status.
This bit indicates the current power supply status (VDD Monitor output).
0: VDD is at or below the VDD monitor threshold.
1: VDD is above the VDD monitor threshold.
Bits5鈥�0: Reserved. Read = Variable. Write = don鈥檛 care.
R/W
RR
RRR
RR
Reset Value
VDMEN
VDDSTAT Reserved Reserved Reserved Reserved Reserved Reserved
Variable
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xFF
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| MAX394EAP+T | IC SWITCH QUAD SPDT 20SSOP |
| MAX314FEPE+ | IC SWITCH QUAD SPST 16DIP |
| VI-BWJ-IY-F4 | CONVERTER MOD DC/DC 36V 50W |
| MAX312FESE+ | IC SWITCH QUAD SPST 16SOIC |
| MAX398CSE+G55 | IC MULTIPLEXER 8X1 16SOIC |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| C8051F349-GMR | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 25 MIPS 32KB USB MCU RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| C8051F349-GQ | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 8-bit 32 KB Flash USB 25 MIPS RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| C8051F349-GQR | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 25 MIPS 32KB USB MCU RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| C8051F34A | 鍒堕€犲晢:SILABS 鍒堕€犲晢鍏ㄧū:SILABS 鍔熻兘鎻忚堪:USB DRIVER CUSTOMIZATION |
| C8051F34A-GM | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 64KB 10ADC 2xUART USB 32Pin MCU RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
鐧�(f膩)甯冪穵鎬ラ噰璩硷紝3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�
