參數(shù)資料
型號: C8051F301-GS
廠商: Silicon Laboratories Inc
文件頁數(shù): 127/178頁
文件大?。?/td> 0K
描述: IC 8051 MCU 8K FLASH 14-SOIC
產(chǎn)品培訓模塊: Serial Communication Overview
標準包裝: 56
系列: C8051F30x
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SMBus(2 線/I²C),UART/USART
外圍設備: POR,PWM,WDT
輸入/輸出數(shù): 8
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 622 (CN2011-ZH PDF)
配用: 336-1444-ND - ADAPTER PROGRAM TOOLSTICK F300
336-1319-ND - REFERENCE DESIGN STEPPER MOTOR
其它名稱: 336-1536-5
C8051F300/1/2/3/4/5
52
Rev. 2.9
The output of Comparator0 can be polled in software, used as an interrupt source, and/or routed to a Port
pin. When routed to a Port pin, the Comparator0 output is available asynchronous or synchronous to the
system clock; the asynchronous output is available even in STOP mode (with no system clock active).
When disabled, the Comparator0 output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic
low state, and its supply current falls to less than 100 nA. See Section “12.1. Priority Crossbar
Decoder” on page 104 for details on configuring the Comparator0 output via the digital Crossbar.
Comparator0 inputs can be externally driven from –0.25 to (VDD) + 0.25 V without damage or upset. The
complete electrical specifications for Comparator0 are given in Table 7.1.
The Comparator0 response time may be configured in software via the CP0MD1-0 bits in register
CPT0MD (see SFR Definition 7.3). Selecting a longer response time reduces the amount of power con-
sumed by Comparator0. See Table 7.1 for complete timing and power consumption specifications.
Positive Hysteresis Voltage
(Programmed with CP0HYP Bits)
Negative Hysteresis Voltage
(Programmed by CP0HYN Bits)
VIN-
VIN+
INPUTS
CIRCUIT CONFIGURATION
+
_
CP0+
CP0-
CP0
VIN+
VIN-
OUT
VOH
Positive Hysteresis
Disabled
Maximum
Positive Hysteresis
Negative Hysteresis
Disabled
Maximum
Negative Hysteresis
OUTPUT
VOL
Figure 7.2. Comparator Hysteresis Plot
The hysteresis of Comparator0 is software-programmable via its Comparator0 Control register (CPT0CN).
The user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive
and negative-going symmetry of this hysteresis around the threshold voltage.
The Comparator0 hysteresis is programmed using Bits3–0 in the Comparator0 Control Register CPT0CN
(shown in SFR Definition 7.1). The amount of negative hysteresis voltage is determined by the settings of
the CP0HYN bits. As shown in Figure 7.2, settings of 20, 10 or 5 mV of negative hysteresis can be pro-
grammed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is
determined by the setting the CP0HYP bits.
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