參數(shù)資料
型號: C8051F300-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 41/178頁
文件大?。?/td> 0K
描述: IC 8051 MCU 8K FLASH 11QFN
產(chǎn)品培訓模塊: Serial Communication Overview
標準包裝: 122
系列: C8051F30x
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SMBus(2 線/I²C),UART/USART
外圍設備: POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 8
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 10-VFDFN 裸露焊盤
包裝: 管件
產(chǎn)品目錄頁面: 623 (CN2011-ZH PDF)
配用: 336-1444-ND - ADAPTER PROGRAM TOOLSTICK F300
336-1351-ND - KIT REF DES TEMP COMPENS RTC
336-1348-ND - KIT STARTER TOOLSTICK
336-1283-ND - KIT REF DESIGN DTMF DECODER
336-1278-ND - KIT TOOL EVAL SYS IN A USB STICK
336-1246-ND - DEV KIT F300/301/302/303/304/305
其它名稱: 336-1245
Rev. 2.9
135
C8051F300/1/2/3/4/5
14.3. Multiprocessor Communications
9-Bit UART mode supports multiprocessor communication between a master processor and one or more
slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or
more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte
in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0.
Setting the MCE0 bit (SCON.5) of a slave processor configures its UART such that when a stop bit is
received, the UART will generate an interrupt only if the ninth bit is logic one (RB80 = 1) signifying an
address byte has been received. In the UART interrupt handler, software will compare the received
address with the slave's own assigned 8-bit address. If the addresses match, the slave will clear its MCE0
bit to enable interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave
their MCE0 bits set and do not generate interrupts on the reception of the following data bytes, thereby
ignoring the data. Once the entire message is received, the addressed slave resets its MCE0 bit to ignore
all transmissions until it receives the next address byte.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple
slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master
processor can be configured to receive all transmissions or a protocol can be implemented such that the
master/slave role is temporarily reversed to enable half-duplex transmission between the original master
and slave(s).
Master
Device
Slave
Device
TX
RX
TX
Slave
Device
RX
TX
Slave
Device
RX
TX
+5V
Figure 14.6. UART Multi-Processor Mode Interconnect Diagram
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參數(shù)描述
C8051F300-GMR 功能描述:8位微控制器 -MCU 8KB 8ADC 11P MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
C8051F300-GS 功能描述:8位微控制器 -MCU 8KB Flash, 8-bit ADC 2%osc RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
C8051F300-GSR 功能描述:8位微控制器 -MCU 8KB 8ADC 2%osc MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
C8051F300P 功能描述:8位微控制器 -MCU PROTO TYPE VERSION IN 14P DIP PACKAGE RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
C8051F300R 功能描述:8位微控制器 -MCU 8 ADC calOSC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT