參數(shù)資料
型號: C8051F236-GQR
廠商: Silicon Laboratories Inc
文件頁數(shù): 40/146頁
文件大?。?/td> 0K
描述: IC 8051 MCU 8K FLASH 48TQFP
產(chǎn)品培訓(xùn)模塊: Serial Communication Overview
標(biāo)準(zhǔn)包裝: 500
系列: C8051F2xx
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 帶卷 (TR)
C8051F2xx
134
Rev. 1.6
17.2.1. Mode 0: 16-bit Counter/Timer with Capture
In this mode, Timer 2 operates as a 16-bit counter/timer with capture facility. A high-to-low transition on the
T2EX input pin causes the 16-bit value in Timer 2 (TH2, TL2) to be loaded into the capture registers
(RCAP2H, RCAP2L).
Timer 2 can use either SYSCLK, SYSCLK divided by 12, or high-to-low transitions on the external T2 input
pin as its clock source when operating in Counter/Timer with Capture mode.
Clearing the C/T2 bit
(T2CON.1) selects the system clock as the input for the timer (divided by one or twelve as specified by the
Timer Clock Select bit T2M in CKCON). When C/T2 is set to logic 1, a high-to-low transition at the T2 input
pin increments the counter/timer register. As the 16-bit counter/timer register increments and overflows
from 0xFFFF to 0x0000, the TF2 timer overflow flag (T2CON.7) is set and an interrupt will occur if the inter-
rupt is enabled.
Counter/Timer with Capture mode is selected by setting the Capture/Reload Select bit CP/RL2 (T2CON.0)
and the Timer 2 Run Control bit TR2 (T2CON.2) to logic 1.
The Timer 2 External Enable EXEN2
(T2CON.3) must also be set to logic 1 to enable a capture. If EXEN2 is cleared, transitions on T2EX will
be ignored.
Figure 17.4. T2 Mode 0 Block Diagram
TL2
TH2
EXEN2
T2EX
TR2
T2
SYSCLK
12
0
1
0
Interrupt
TCLK
RCAP2L
RCAP2H
Capture
T2C
O
N
RCLK
TCLK
EXF2
EXEN2
TR2
C/T2
CP/RL2
TF2
CKCON
T
2
M
T
1
M
T
0
M
PORT0
MUX
PORT0
MUX
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