參數(shù)資料
型號(hào): C8051F226
廠商: Silicon Laboratories Inc
文件頁數(shù): 116/146頁
文件大?。?/td> 0K
描述: IC 8051 MCU 8K FLASH 48TQFP
標(biāo)準(zhǔn)包裝: 250
系列: C8051F2xx
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 32x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 托盤
C8051F2xx
Rev. 1.6
71
9.3.1. Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved
bits should be set to logic 0. Future product versions may use these bits to implement new features in
which case the reset value of the bit will be logic 0, selecting the feature’s default state. Detailed descrip-
tions of the remaining SFRs are included in the sections of the datasheet associated with their correspond-
ing system function.
SFR Definition 9.1. SP: Stack Pointer
Bits 7–0: SP: Stack Pointer.
The stack pointer holds the location of the top of the stack. The stack pointer is incremented
before every PUSH operation. The SP register defaults to 0x07 after reset.
SFR Definition 9.2. DPL: Data Pointer Low Byte
Bits 7–0: DPL: Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed RAM.
SFR Definition 9.3. DPH: Data Pointer High Byte
Bits 7–0: DPH: Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed RAM.
R/W
Reset Value
00000111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x81
R/W
Reset Value
00000111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x81
R/W
Reset Value
00000111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x81
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