參數(shù)資料
型號： C8051F221
廠商： Silicon Laboratories Inc
文件頁數(shù)： 95/146頁
文件大?。?/td> 0K
描述： IC 8051 MCU 8K FLASH 32LQFP
標(biāo)準(zhǔn)包裝： 250
系列： C8051F2xx
核心處理器： 8051
芯體尺寸： 8-位
速度： 25MHz
連通性： SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，WDT
輸入/輸出數(shù)： 22
程序存儲器容量： 8KB（8K x 8）
程序存儲器類型： 閃存
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 22x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 32-LQFP
包裝： 托盤
C8051F2xx
52
Rev. 1.6
8.
Comparators
The MCU has two on-board voltage comparators as shown in Figure 8.1. The inputs of each Comparator
are available at the package pins. The output of each comparator is optionally available at port1 by config-
uring (see Section 14). When assigned to package pins, each comparator output can be programmed to
operate in open drain or push-pull modes (see section 14.2).
The hysteresis of each comparator is software-programmable via its respective Comparator Control Regis-
ter (CPT0CN, CPT1CN).
The user can program both the amount of hysteresis voltage (referred to the
input voltage) and the positive-going and negative-going symmetry of this hysteresis around the threshold
voltage. The output of the comparator can be polled in software, or can be used as an interrupt source.
Each comparator can be individually enabled or disabled (shutdown). When disabled, the comparator out-
put (if assigned to a Port I/O pin via the Port1 MUX) defaults to the logic low state and its interrupt capabil-
ity is suspended. Comparator inputs can be externally driven from –0.25 V to (VDD) + 0.25 V without
damage or upset.
The Comparator 0 hysteresis is programmed using bits 3–0 in the Comparator 0 Control Register CPT0CN
(shown in SFR Definition 8.1). The amount of negative hysteresis voltage is determined by the settings of
the CP0HYN bits. As shown in Figure 8.2, settings of 10, 4 or 2 mV of negative hysteresis can be pro-
grammed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is
determined by the setting the CP0HYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Inter-
rupt enable and priority control, see Section 9.4). The CP0FIF flag is set upon a Comparator 0 falling-edge
interrupt, and the CP0RIF flag is set upon the Comparator 0 rising-edge interrupt. Once set, these bits
remain set until cleared by the user software. The Output State of Comparator 0 can be obtained at any
time by reading the CP0OUT bit.
Comparator 0 is enabled by setting the CP0EN bit, and is disabled by
clearing this bit. Note there is a 20 mS power on time between setting CP0EN and the output stabilizing.
Comparator 0 can also be programmed as a reset source. For details, see Section 11. The operation of
Comparator 1 is identical to that of Comparator 0, except the Comparator 1 is controlled by the CPT1CN
Register (SFR Definition 8.2). Also, Comparator 1 can not be programmed as a reset source. The com-
plete electrical specifications for the Comparators are given in Table 8.1.
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