2002 Cygnal Integrated Products, Inc.
DS007-0.4-NOV02
Page 11
C8051F060/1/2/3
A
Figure 12.22. EIE2: Extended Interrupt Enable 2 .................................................................149
Figure 12.23. EIP1: Extended Interrupt Priority 1.................................................................150
Figure 12.24. EIP2: Extended Interrupt Priority 2.................................................................151
Figure 12.25. PCON: Power Control.....................................................................................153
Advanced
Information
Figure 8.1. DAC Functional Block Diagram.........................................................................99Figure 8.2. DAC0H: DAC0 High Byte Register .................................................................101
Figure 8.3. DAC0L: DAC0 Low Byte Register ..................................................................101
Figure 8.4. DAC0CN: DAC0 Control Register...................................................................102
Figure 8.5. DAC1H: DAC1 High Byte Register .................................................................103
Figure 8.6. DAC1L: DAC1 Low Byte Register ..................................................................103
Figure 8.7. DAC1CN: DAC1 Control Register...................................................................104
9. VOLTAGE REFERENCE 2 (C8051F060/2).....................................................................107
Figure 9.1. Voltage Reference Functional Block Diagram..................................................107
Figure 9.2. REF2CN: Reference Control Register 2 ...........................................................108
10. VOLTAGE REFERENCE 2 (C8051F061/3) ....................................................................109
Figure 10.1. Voltage Reference Functional Block Diagram .................................................109
Figure 10.2. REF2CN: Reference Control Register 2...........................................................110
11. COMPARATORS................................................................................................................111
Figure 11.1. Comparator Functional Block Diagram............................................................111
Figure 11.2. Comparator Hysteresis Plot...............................................................................112
Figure 11.3. CPTnCN: Comparator 0, 1, and 2 Control Register..........................................114
Figure 11.4. CPTnMD: Comparator Mode Selection Register .............................................115
12. CIP-51 MICROCONTROLLER........................................................................................117
Figure 12.1. CIP-51 Block Diagram.....................................................................................117
Figure 12.2. Memory Map.....................................................................................................123
Figure 12.3. SFR Page Stack.................................................................................................126
Figure 12.4. SFR Page Stack While Using SFR Page 0x0F To Access Port 5 .....................127
Figure 12.5. SFR Page Stack After ADC2 Window Comparator Interrupt Occurs..............128
Figure 12.6. SFR Page Stack Upon PCA Interrupt Occurring During an ADC2 ISR...........129
Figure 12.7. SFR Page Stack Upon Return From PCA Interrupt..........................................130
Figure 12.8. SFR Page Stack Upon Return From ADC2 Window Interrupt.........................131
Figure 12.9. SFRPGCN: SFR Page Control Register............................................................132
Figure 12.10. SFRPAGE: SFR Page Register.......................................................................132
Figure 12.11. SFRNEXT: SFR Next Register.......................................................................133
Figure 12.12. SFRLAST: SFR Last Register ........................................................................133
Figure 12.13. SP: Stack Pointer.............................................................................................140
Figure 12.14. DPL: Data Pointer Low Byte ..........................................................................140
Figure 12.15. DPH: Data Pointer High Byte.........................................................................140
Figure 12.16. PSW: Program Status Word............................................................................141
Figure 12.18. B: B Register...................................................................................................142
Figure 12.19. IE: Interrupt Enable.........................................................................................146
Figure 12.20. IP: Interrupt Priority........................................................................................147