2002 Cygnal Integrated Products, Inc.
DS007-0.4-NOV02
Page 13
C8051F060/1/2/3
A
Figure 20.8. SPI0CKR: SPI0 Clock Rate Register................................................................243
Figure 20.9. SPI0DAT: SPI0 Data Register..........................................................................244
Figure 20.10. SPI Slave Timing (CKPHA = 0).....................................................................245
Figure 20.11. SPI Slave Timing (CKPHA = 1).....................................................................245
Advanced
Information
Figure 17.17. P3: Port3 Data Register...................................................................................206Figure 17.18. P3MDOUT: Port3 Output Mode Register.......................................................206
Figure 17.19. P4: Port4 Data Register...................................................................................209
Figure 17.20. P4MDOUT: Port4 Output Mode Register.......................................................209
Figure 17.21. P5: Port5 Data Register...................................................................................210
Figure 17.22. P5MDOUT: Port5 Output Mode Register.......................................................210
Figure 17.23. P6: Port6 Data Register...................................................................................211
Figure 17.24. P6MDOUT: Port6 Output Mode Register.......................................................211
Figure 17.25. P7: Port7 Data Register...................................................................................212
Figure 17.26. P7MDOUT: Port7 Output Mode Register.......................................................212
18. CONTROLLER AREA NETWORK (CAN0)..................................................................213
Figure 18.1. CAN Controller Diagram..................................................................................214
Figure 18.2. Typical CAN Bus Configuration.......................................................................214
Figure 18.3. CAN0DATH: CAN Data Access Register High Byte......................................220
Figure 18.4. CAN0DATL: CAN Data Access Register Low Byte.......................................220
Figure 18.5. CAN0ADR: CAN Address Index Register.......................................................221
Figure 18.6. CAN0CN: CAN Control Register.....................................................................221
Figure 18.7. CAN0TST: CAN Test Register.........................................................................222
Figure 18.8. CAN0STA: CAN Status Register .....................................................................222
19. SYSTEM MANAGEMENT BUS / I2C BUS (SMBUS0).................................................223
Figure 19.1. SMBus0 Block Diagram ...................................................................................223
Figure 19.2. Typical SMBus Configuration ..........................................................................224
Figure 19.3. SMBus Transaction...........................................................................................225
Figure 19.4. Typical Master Transmitter Sequence...............................................................226
Figure 19.5. Typical Master Receiver Sequence...................................................................226
Figure 19.6. Typical Slave Transmitter Sequence.................................................................227
Figure 19.7. Typical Slave Receiver Sequence .....................................................................227
Figure 19.8. SMB0CN: SMBus0 Control Register ...............................................................229
Figure 19.9. SMB0CR: SMBus0 Clock Rate Register..........................................................230
Figure 19.10. SMB0DAT: SMBus0 Data Register ...............................................................231
Figure 19.11. SMB0ADR: SMBus0 Address Register..........................................................231
Figure 19.12. SMB0STA: SMBus0 Status Register..............................................................232
20. ENHANCED SERIAL PERIPHERAL INTERFACE (SPI0).........................................235
Figure 20.1. SPI Block Diagram............................................................................................235
Figure 20.2. Multiple-Master Mode Connection Diagram....................................................238
Figure 20.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram ....238
Figure 20.5. Data/Clock Timing Diagram.............................................................................240
Figure 20.6. SPI0CFG: SPI0 Configuration Register............................................................241