參數(shù)資料
型號: C8051F006-GQR
廠商: Silicon Laboratories Inc
文件頁數(shù): 129/171頁
文件大小: 0K
描述: IC 8051 MCU 32K FLASH 48TQFP
產(chǎn)品培訓模塊: Serial Communication Overview
標準包裝: 500
系列: C8051F00x
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SMBus(2 線/I²C),SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 帶卷 (TR)
配用: 336-1188-ND - DEV KIT FOR F005/006/007
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
9.
VOLTAGE REFERENCE
The voltage reference circuit consists of a 1.2V, 15ppm/
C (typical) bandgap voltage reference generator and a
gain-of-two output buffer amplifier. The reference voltage on VREF can be connected to external devices in the
system, as long as the maximum load seen by the VREF pin is less than 200
A to AGND (see Figure 9.1).
If a different reference voltage is required, an external reference can be connected to the VREF pin and the internal
bandgap and buffer amplifier disabled in software. The external reference voltage must still be less than AV+ -
0.3V. The Reference Control Register, REF0CN (defined in Figure 9.2), provides the means to enable or disable
the bandgap and buffer amplifier. The BIASE bit in REF0CN enables the bias circuitry for the ADC and DACs
while the REFBE bit enables the bandgap reference and buffer amplifier which drive the VREF pin.
When
disabled, the supply current drawn by the bandgap and buffer amplifier falls to less than 1uA (typical) and the
output of the buffer amplifier enters a high impedance state. If the internal bandgap is used as the reference voltage
generator, BIASE and REFBE must both be set to 1. If an external reference is used, REFBE must be set to 0 and
BIASE must be set to 1. If neither the ADC nor the DAC are being used, both of these bits can be set to 0 to
conserve power. The electrical specifications for the Voltage Reference are given in Table 9.1.
The temperature sensor connects to the highest order input of the A/D converter’s input multiplexer (see Figure 5.1
and Figure 5.5 for details). The TEMPE bit within REF0CN enables and disables the temperature sensor. While
disabled, the temperature sensor defaults to a high impedance state and any A/D measurements performed on the
sensor while disabled result in meaningless data.
Figure 9.1. Voltage Reference Functional Block Diagram
Bias
Generator
(to ADC
and DAC)
VREF
EN
(to Analog Mux)
RLOAD
AGND
External Equivalent
Load Circuit
AGND
R1
AV+
External
Voltage
Reference
Circuit
Temp
Sensor
EN
200uA
(max)
(Bias to ADC
and DAC)
REF
0
CN
TEMPE
BIASE
REFBE
2.4V
Reference
EN
AGND
Rev. 1.7
60
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