參數(shù)資料
型號(hào): C6007BT
英文描述: 8-INPUT NOR/OR GATE
中文描述: 雜項(xiàng)時(shí)鐘發(fā)生器|采用TSSOP | 16PIN |塑料
文件頁(yè)數(shù): 3/6頁(yè)
文件大?。?/td> 35K
代理商: C6007BT
Document # 38-07101
Rev. **
Page 3 of 6
C6007B
Maximum Ratings
Maximum Input Voltage Relative to VSS:VSS – 0.3V
Maximum Input Voltage Relative to VDD:VDD + 0.3V
Storage Temperature:
Operating Temperature:
Maximum ESD protection
Maximum Power Supply:
Operating Voltage:
-65
o
to +150
o
C
-10
o
to +75
o
C
2KV
5.5V
3.0 – 3.6V
This device contains circuitry to protect the inputs
against damage due to high static voltages or
electric field; however, precautions should be taken
to avoid application of any voltage higher than the
maximum rated voltages to this circuit. For proper
operation, Vin and Vout should be constrained to
the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an
appropriate logic voltage level (either VSS or
VDD).
DC Parameters
(VDD = 3.3V +/- 10%, TA = -10
°
C to + 75
°
C)
Characteristic
Dynamic Supply Current
Output Low Voltage
Output High Voltage
Crystal pin capacitance
Symbol
Idd3.3V
VOL
VOH
Cxtal
Min
-
-
2.4
-
Typ
18
-
-
-
Max
27
0.4
-
5
Units
mA
V
V
pF
Conditions
No output load
IOL = 4.0mA
IOH = 4.0mA
Capacitance at XTI,XTO
AAC Parameters
(Note 1)
Parameter
Frequency error, all outputs
Rise Time
Symbol
F
ERR
T
R
Min
-
-
Typ
-
3
Max
0
5
Units
PPM
nsec
Conditions
XTI= 27.00MHz
All clocks at rated load,
Note 2
All clocks at rated load,
Note 2
All Output Clocks, Note 3
All clocks at rated load,
Note 3
Cycle to cycle jitter
(Peak -maximum)
All clocks at rated load
Note 3
Fall Time
T
F
-
3
5
nsec
Power up to Stable Output
Clock Duty Cycle
(all output clocks)
Clock Jitter
(33-1Out,-2Out,-3Out)
Clock Jitter
(REFOUT)
Notes:
1. Parameters are guaranteed by design and characterization. Not 100% tested in production. All
parameters specified with fully loaded outputs.
2. Measured between 0.2*VDD and 0.8*VDD Volts
3. Triggering is done at 1.5 Volts
T
PU
T
DC1
-
-
3
55
msec
%
45
50
T
j1
-
150
200
psec
T
j2
-
220
350
psec
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