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參數(shù)資料
| 型號： | C6006AZ |
| 英文描述： | 4 BIT D TYPE REGISTERS |
| 中文描述： | 雜項(xiàng)時(shí)鐘發(fā)生器|專科| 8引腳|塑料 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 39K |
| 代理商： | C6006AZ |
C6006
Clock Generator IC for MD Audio System
Approved Product
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134 Tel 408-943-2600
Document#: 38-07100 Rev. **
9/15/2000
Page 3 of
6
Maximum Ratings
Maximum Input Voltage Relative to VSS: VSS – 0.3V
Maximum Input Voltage Relative to VDD: VDD + 0.3V
Storage Temperature:
Operating Temperature:
Maximum Power Supply:
Operating Voltage:
-65
o
to +150
o
C
-10
o
to +70
o
C
5.5V
3.0 – 3.6V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
DC Parameters
(VDD = 3.3V +/- 10%, TA = -10
o
to +70
o
C)
Characteristic
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Dynamic Supply Current
Output Low Voltage
Output High Voltage
XIN/XOUT Capacitors
Note1:
Applicable to input signal.
Note2:
Although internal pull-up resistors have a typical value of 240K, this value may vary between 200K and
500K.
Symbol
VIL
VIH
IIL
IIH
Idd3.3V
VOL
VOH
CL1,2
Min
-
2.0
-100
-
-
-
2.4
-
Typ
-
-
-
-
20
-
-
23
Max
0.8
-
-
10
35
0.4
-
-
Units
Vdc
Vdc
μA
μA
mA
V
V
pF
Conditions
Note 1
For internal Pull-up resistors, Note 1
and Note 2
No output load
IOL = 4.0 mA
IOH = 3.0 mA
AAC Parameters
Parameter
Rise Time
Fall Time
Power up to Stable Output
Clock Duty Cycle
Clock Jitter, @CLK1
Symbol
T
R
T
F
T
PU
T
DC1
T
j1
Min
-
-
-
40
-
Typ
-
-
-
50
-
Max
4
4
3
60
150
Units
nSec
nSec
mSec
%
pSec
Conditions
All clocks at rated load, Note 2
All clocks at rated load, Note 2
All Output Clocks, Note 3
All clocks at rated load, Note 3
Cycle to cycle jitter
Note 2, Note 3
Clock Jitter, @CLK2
Notes:
1. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters
specified with fully loaded outputs.
2. Measured between 0.2*VDD and 0.8*VDD Volts.
3. Triggering is done at 1.5 Volts.
4. All output has 15pf load.
T
j2
-
-
250
psec
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