參數(shù)資料
型號(hào)： C509-L
廠商： SIEMENS AG
元件分類： 8位微控制器
英文描述： 8-Bit CMOS Microcontroller
中文描述： 8位CMOS微控制器
文件頁(yè)數(shù)： 63/74頁(yè)
文件大?。?/td> 1607K
代理商： C509-L
C509-L
Semiconductor Group
62
Power Saving Modes
The C509-L provides three power saving modes in which power consumption can be significantly
reduced.
–
Idle mode
The CPU is gated off from the oscillator. All peripherals are still provided with the clock and
are able to work.
–
Power down mode
The operation of the C509-L is completely stopped and the oscillator is turned off. This mode
is used to save the contents of the internal RAM with a very low standby current. Power down
mode can be entered by software or by hardware (pin HWPD).
–
Slow-down mode
The controller keeps up the full operating functionality, but its normal clock frequency is
internally divided by eight. This slows down all parts of the controller, the CPU and all
peripherals, to 1/8 th of their normal operating frequency. Slowing down the frequency greatly
reduces power consumption.
Table 14
gives a general overview of the entry and exit procedures of the power saving modes.
In the power down mode of operation,
V
CC
can be reduced to minimize power consumption. It must
be ensured, however, that
V
CC
is not reduced before the power down mode is invoked, and that
V
CC
is restored to its normal operating level, before the power down mode is terminated.
If e.g. the idle mode is left through an interrupt, the microcontroller state (CPU, ports, peripherals)
remains preserved. If a power saving mode is left by a hardware reset, the microcontroller state is
disturbed and replaced by the reset state of the C509-L.
Table 14
Power Saving Modes Overview
Mode
Entering
2-Instruction
Example
Leaving by
Remarks
Idle mode
ORL PCON, #01H
ORL PCON, #20H
Ocurrence of an
interrupt from a
peripheral unit
CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with
clock
Hardware Reset
Software
Power-Down Mode
Hardware
Power-Down Mode
ORL PCON, #02H
ORL PCON, #40H
Hardware Reset
Oscillator is stopped;
contents of on-chip RAM and
SFR’s are maintained;
Low level at pin
HWPD
High level at pin
HWPD
Slow Down Mode
ORL PCON,#10H
ANL PCON,#0EFH
or
Hardware Reset
Oscillator frequency is
reduced to 1/8 of its nominal
frequency
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