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參數(shù)資料
| 型號： | C508 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Previous Vectron Model Numbers |
| 中文描述： | 前Vectron型號 |
| 文件頁數(shù)： | 55/93頁 |
| 文件大?。?/td> | 1204K |
| 代理商： | C508 |
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C508
Data Sheet
51
2000-08
Fail Save Mechanisms
The C508 offers enhanced fail save mechanisms, which allow an automatic recovery
from software or hardware failure:
– a programmable watchdog timer (WDT), with variable time-out period from 153.6
μ
s
to 314.573 ms at
f
OSC
= 10 MHz.
– an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the
microcontroller into reset state in case the on-chip oscillator fails; it also provides the
clock for a fast internal reset after power-on.
Programmable Watchdog Timer
To protect the system against software failure, the user’s program must clear this
watchdog within a previously programmed time period. If the software fails to do this
periodical refresh of the watchdog timer, an internal reset will be initiated. The software
can be designed so that the watchdog times out if the program does not work properly.
It also times out if a software error is based on hardware-related problems.
The Watchdog Timer in the C508 is a 15-bit timer, which is incremented by a count rate
of
f
OSC
/6 upto
f
OSC
/96. The machine clock of the C508 is divided by two prescalers, a
divide-by-two and a divide-by-16 prescaler. To program the Watchdog Timer overflow
rate, the upper 7 bits of the Watchdog Timer can be written.
Figure 26
shows the block
diagram of the Watchdog Timer unit.
Figure 26
Block Diagram of the Programmable Watchdog Timer
MCS04087
f
OSC
/3
WDTL
0
7
WDTH
14
8
7
0
6
WDTREL (86
H
)
÷ 16
÷ 2
OWDS
WDTS
-
-
-
-
-
-
-
WDT
-
-
-
-
-
-
-
SWDT
-
-
-
-
-
-
Control Logic
WDTPSEL
IP0 (A9
H
)
WDT Reset-Request
External HW Reset
IEN0 (A8
H
)
IEN1 (B8
H
)
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