參數(shù)資料
型號(hào)： C505
廠商： SIEMENS AG
元件分類： 8位微控制器
英文描述： 8-Bit CMOS Microcontroller
中文描述： 8位CMOS微控制器
文件頁(yè)數(shù)： 53/88頁(yè)
文件大?。?/td> 1224K
代理商： C505
C505/C505C/C505A/C505CA
Data Sheet
49
12.00
Power Saving Modes
The C505 provides two basic power saving modes, the idle mode and the power down mode.
Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate
in normal operating mode and it can be also used for further power reduction in idle mode.
–
Idle mode
In the idle mode the main oscillator of the C505 continues to run, but the CPU is gated off from
the clock signal. All peripheral units are further provided with the clock. The CPU status is
preserved in its entirety. The idle mode can be terminated by any enabled interrupt of a
peripheral unit or by a hardware reset.
–
Power down mode
The operation of the C505 is completely stopped and the oscillator is turned off. This mode is
used to save the contents of the internal RAM with a very low standby current. Power down
mode is entered by software and can be left by reset or by a short low pulse at pin P3.2/
INT0.or P4.1/RXDC.
–
Slow down mode
The controller keeps up the full operating functionality, but its normal clock frequency is
internally divided by 32. This slows down all parts of the controller, the CPU and all
peripherals, to 1/32-th of their normal operating frequency. Slowing down the frequency
significantly reduces power consumption.
In the power down mode of operation,
V
DD
can be reduced to minimize power consumption. It must
be ensured, however, that
V
DD
is not reduced before the power down mode is invoked, and that
V
DD
is restored to its normal operating level, before the power down mode is terminated.
Table 10
gives
a general overview of the entry and exit procedures of the power saving modes.
Table 10
Power Saving Modes Overview
Mode
Entering
(Instruction
Example)
ORL PCON, #01H
ORL PCON, #20H
Leaving by
Remarks
Idle Mode
Ocurrence of an
interrupt from a
peripheral unit
Hardware Reset
CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with
clock
Oscillator is stopped;
contents of on-chip RAM and
SFR
’
s are maintained;
Power Down Mode
ORL PCON, #02H
ORL PCON, #40H
Hardware Reset
Short low pulse at
pin P3.2/INT0 or
P4.1/RXDC
ANL PCON,#0EFH
or
Hardware Reset
Slow Down Mode
ORL PCON,#10H
Oscillator frequency is
reduced to 1/32 of its nominal
frequency
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