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參數(shù)資料
| 型號： | C161PI |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | DC/DC變換器 |
| 英文描述： | RSD Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 3.3V; Power: 1W; 1kVDC and 3kVDC Isolation Options; Approved for Medical Applications; Suitable for Automated Assembly; 8, 10 and 12 pin Pinning Style Options; Optional Continuous Short Circuit Protected; Efficiency to 85% |
| 中文描述： | 16位單片機 |
| 文件頁數(shù)： | 76/82頁 |
| 文件大?。?/td> | 991K |
| 代理商： | C161PI |
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&3,
Data Sheet
74
1999-07
AC Characteristics
CLKOUT and READY (Standard Supply Voltage Range)
(Operating Conditions apply)
Parameter
Symbol
Max. CPU Clock
= 25 MHz
min.
40
14
10
–
–
0 +
W
A
Variable CPU Clock
1 / 2TCL = 1 to 25 MHz
min.
2TCL
TCL – 6
TCL – 10
–
–
0 +
W
A
Unit
max.
40
–
–
4
4
10 +
W
A
max.
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
CLKOUT rising edge to
ALE falling edge
Synchronous READY
setup time to CLKOUT
Synchronous READY
hold time after CLKOUT
Asynchronous READY
low time
Asynchronous READY
setup time
1)
Asynchronous READY
hold time
1)
Async. READY hold time
after RD, WR high
(Demultiplexed Bus)
2)
W
29
W
30
W
31
W
32
W
33
W
34
CC
CC
CC
CC
CC
CC
2TCL
–
–
4
4
10 +
W
A
ns
ns
ns
ns
ns
ns
W
35
SR
14
–
14
–
ns
W
36
SR
4
–
4
–
ns
W
37
SR
54
–
2TCL +
W
58
–
ns
1) These timings are given for test purposes only, in order to assure recognition at a specific clock edge.
W
58
SR
14
–
14
–
ns
W
59
SR
4
–
4
–
ns
2) Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This
adds even more time for deactivating READY.
The 2
W
A
and
W
C
refer to the next following bus cycle,
W
F
refers to the current bus cycle.
The maximum limit for
W
60
must be fulfilled if the next following bus cycle is READY controlled.
W
60
SR
0
0
+ 2
W
A
+
W
C
+
W
F
2)
0
TCL - 20
+ 2
W
A
+
W
C
+
W
F
2)
ns
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