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參數(shù)資料
| 型號： | C161CS-32R |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 16-Bit Single-Chip Microcontroller |
| 中文描述： | 16位單片機 |
| 文件頁數(shù)： | 19/89頁 |
| 文件大?。?/td> | 876K |
| 代理商： | C161CS-32R |
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C161CS/JC/JI-32R
C161CS/JC/JI-L
Data Sheet
15
V3.0, 2001-01
Functional Description
The architecture of the C161CS/JC/JI combines advantages of both RISC and CISC
processors and of advanced peripheral subsystems in a very well-balanced way. In
addition the on-chip memory blocks allow the design of compact systems with maximum
performance.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the C161CS/JC/JI.
Note: All time specifications refer to a CPU clock of 25 MHz
(see definition in the AC Characteristics section).
Figure 3
Block Diagram
The program memory, the internal RAM (IRAM) and the set of generic peripherals are
connected to the CPU via separate buses. A fourth bus, the XBUS, connects external
resources as well as additional on-chip resoures, the X-Peripherals (see
Figure 3
).
The XBUS resources (XRAM, CAN, SDLM, IIC, ASC1) of the C161CS/JC/JI can be
enabled during initialization by setting the general X-Peripheral enable bit XPEN
(SYSCON.2).
If the X-Peripherals remain disabled they consume neither address space nor port pins.
C166-Core
CPU
P
Interrupt Bus
XTAL
Osc / PLL
RTC
WDT
32
16
Interrupt Controller
16-Level
Priority
PEC
External Instr. / Data
GPT
T2
T3
T4
T5
T6
SSC
(SPI)
BRGen
ASC0
(USART)
BRGen
ADC
10-Bit
12
Channels
CCOM1
T0
T1
CCOM2
T7
T8
EBC
XBUS Control
External Bus
Control
IRAM
Internal
RAM
2 KByte
D
ProgMem
ROM
256 KByte
Data
Data
16
16
16
CAN/SDLM
2.0B act. / Cl.B
Instr. / Data
Port 0
XRAM
8 KByte
P
8
8
Port 1
16
12
16
Port 5
Port 3
15
Port 7
4
Port 9
6
P
8
Peripheral Data Bus
ASC1
(USART)
IIC
400 KBd, 2 Ch.
16
O
MCB04323_1CSR
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