參數(shù)資料
型號(hào)： BX80546PG3200E
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 3200 MHz, MICROPROCESSOR, CPGA478
封裝： 1.27 MM PITCH, FLIP CHIP, MICRO PGA-478
文件頁(yè)數(shù)： 11/80頁(yè)
文件大小： 1845K
代理商： BX80546PG3200E
Datasheet
19
Electrical Specifications
2.6
Asynchronous GTL+ Signals
Legacy input signals (such as A20M#, IGNNE#, INIT#, SMI#, SLP#, and STPCLK#) use CMOS
input buffers. All of these signals follow the same DC requirements as GTL+ signals; however, the
outputs are not actively driven high (during a logical 0-to-1 transition) by the processor. These
signals do not have setup or hold time specifications in relation to BCLK[1:0].
2.7
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is
recommended that the processor be first in the TAP chain and followed by any other components
within the system. A translation buffer should be used to connect to the rest of the chain unless one
of the other components is capable of accepting an input of the appropriate voltage level. Similar
considerations must be made for TCK, TMS, TRST#, TDI, and TDO. Two copies of each signal
may be required, with each driving a different voltage level.
Table 5.
Signal Characteristics
Signals with R
TT
Signals with No R
TT
A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#,
BNR#, BOOTSELECT1, BPRI#, D[63:0]#, DBI[3:0]#,
DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#,
OPTIMIZED/COMPAT#1, PROCHOT#, REQ[4:0]#,
RS[2:0]#, RSP#, TRDY#
NOTES:
1.
The OPTIMIZED/COMPAT# and BOOTSELECT pins have a 500–5000
pull-up to V
CCVID rather than RTT.
A20M#, BCLK[1:0], BPM[5:0]#, BR0#, BSEL[1:0],
COMP[1:0], FERR#/PBE#, IERR#, IGNNE#, INIT#,
LINT0/INTR, LINT1/NMI, PWRGOOD, RESET#,
SKTOCC#, SLP#, SMI#, STPCLK#, TDO,
TESTHI[12:0], THERMDA, THERMDC,
THERMTRIP#, VID[5:0], VIDPWRGD,
GTLREF[3:0], TCK, TDI, TRST#, TMS
Open Drain Signals2
2.
Signals that do not have R
TT, nor are actively driven to their high-voltage level.
BSEL[1:0], VID[5:0], THERMTRIP#, FERR#/PBE#,
IERR#, BPM[5:0]#, BR0#, TDO
Table 6.
Signal Reference Voltages
GTLREF
VCC/2
VCCVID/2
BPM[5:0]#, LINT0/INTR, LINT1/NMI, RESET#, BINIT#, BNR#,
HIT#, HITM#, MCERR#, PROCHOT#, BR0#, A[35:0]#, ADS#,
ADSTB[1:0]#, AP[1:0]#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#,
DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#,
LOCK#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#
A20M#, IGNNE#, INIT#,
PWRGOOD1, SLP#,
SMI#, STPCLK#, TCK1,
TDI1, TMS1, TRST#1
NOTES:
1.
These signals also have hysteresis added to the reference voltage. See Table 14 for more information.
VIDPWRGD,
BOOTSELECT,
OPTIMIZED/
COMPAT#
相關(guān)PDF資料
PDF描述
BU-61580G0-160W 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70
BU-61580G5-110S 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70
BU-61580S0-110W 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70
BU-61580S1-140Y 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70
BU-61580S2-170K 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
BX80546PG3200E S L8K2 制造商:Intel 功能描述:
BX80546PG3400E 制造商:Intel 功能描述:MPU PENTIUM 4 PROCESSOR NETBURST 90NM 3.4GHZ - Boxed Product (Development Kits)
BX80546RE2130C S L93R 制造商:Intel 功能描述:MPU CELERON D RISC 64BIT 90NM 2.13GHZ 478PIN FCUPGA4 - Boxed Product (Development Kits)
BX80546RE2400C 制造商:Intel 功能描述:MPU CELERON D PROCESSOR 320 RISC 64-BIT 90NM 2.4GHZ - Boxed Product (Development Kits)
BX80546RE2400C S L87J 制造商:Intel 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*