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參數(shù)資料
| 型號： | BX80536GE2133FJ |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2130 MHz, MICROPROCESSOR, CPGA478 |
| 封裝： | FLIP CHIP, MICRO PGA-478 |
| 文件頁數(shù)： | 11/30頁 |
| 文件大?。?/td> | 887K |
| 代理商： | BX80536GE2133FJ |
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Datasheet
19
Electrical Specifications
3.5
Signal Terminations and Unused Pins
All RSVD (RESERVED) pins must remain unconnected. Connection of these pins to VCC, VSS, or
to any other signal (including each other) can result in component malfunction or incompatibility
with future Pentium M Processors. See Section 4.1 for a pin listing of the processor and the
location of all RSVD pins.
For reliable operation, always connect unused inputs or bidirectional signals to an appropriate
signal level. Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is
provided on the processor silicon. Unused active high inputs should be connected through a resistor
to ground (VSS). Unused outputs can be left unconnected.
The TEST1 and TEST2 pins must have a stuffing option connection to VSS separately via 1 k,
pull-down resistors.
3.6
FSB Frequency Select Signals (BSEL[1:0])
The BSEL[1:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]).
These signals should be connected to the clock chip and Intel 915PM/GM and Intel 915GMS
Express chipset on the platform. The BSEL encoding for BCLK[1:0] is shown in Table 3-2.
3.7
FSB Signal Groups
In order to simplify the following discussion, the FSB signals have been combined into groups by
buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference
level. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as well as the
AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group
as well as the AGTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify two sets of
timing parameters. One set is for common clock signals which are dependant upon the rising edge
of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals
which are relative to their respective strobe lines (data and address) as well as the rising edge of
BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at
any time during the clock cycle. Table 3-3 identifies which signals are common clock, source
synchronous, and asynchronous.
Table 3-2. BSEL[1:0] Encoding for BCLK Frequency
BSEL[1]
BSEL[0]
BCLK Frequency
L
H
100 MHz
L
133 MHz
H
L
RESERVED
H
RESERVED
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| BX80536NC1700EJ | 制造商:Intel 功能描述:MPU CELERON PROCESSOR 390 RISC 64-BIT 90NM 1.7GHZ 1.05V - Boxed Product (Development Kits) |
| BX80537T5500 S L9SH | 制造商:Intel 功能描述:MPU Core?2 Duo Processor T5500 64-Bit 65nm 1.66GHz 1.05V 478-Pin FCPGA6 |
| BX80537T5500 S L9U4 | 制造商:Intel 功能描述:MPU Core?2 Duo Processor T5500 64-Bit 65nm 1.66GHz 1.05V 478-Pin uFCPGA |
| BX80537T5600 S L9SG | 制造商:Intel 功能描述:MPU Core?2 Duo Processor T5600 64-Bit 65nm 1.83GHz 1.05V 478-Pin FCPGA6 |
| BX80537T5600 S L9U3 | 制造商:Intel 功能描述:MPU Core?2 Duo Processor T5600 64-Bit 65nm 1.83GHz 1.05V 478-Pin uFCPGA |
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