
Features
6-8
Intel Xeon Processor MP with up to 2MB L3 Cache
6.4.2
Scratch EEPROM
Also available in the memory component on the Intel Xeon processor MP on the 0.13 micron
process processor in INT-mPGA package, is an EEPROM which may be used for other data at the
system or processor vendor’s discretion. The data in this EEPROM, once programmed, can be
write-protected by asserting the active-high SM_WP signal. This signal has a weak pull-down
(10 k
) to allow the EEPROM to be programmed in systems with no implementation of this
signal. The Scratch EEPROM resides in the upper half of the memory component (addresses 80 -
FFh). The lower half comprises the Processor Information ROM (address 00 - 7Fh), which is
permanently write protected by Intel.
6.4.3
PIROM and Scratch EEPROM Supported SMBus
Transactions
The Processor Information ROM (PIR) responds to two SMBus packet types: Read Byte and Write
Byte. However, since the PIR is write-protected, it will acknowledge a Write Byte command but
ignore the data. The Scratch EEPROM responds to Read Byte and Write Byte commands.
Table 36diagrams the Read Byte command.
Table 37 diagrams the Write Byte command. Following a write
cycle to the scratch ROM, software must allow a minimum of 10 ms before accessing either ROM
of the processor.
In the tables, ‘S’ represents the SMBus start bit, ‘P’ represents a stop bit, ‘R’ represents a read bit,
‘W’ represents a write bit, ‘A’ represents an acknowledge (ACK), and ‘///’ represents a negative
acknowledge (NACK). The shaded bits are transmitted by the Processor Information ROM or
Scratch EEPROM, and the bits that aren’t shaded are transmitted by the SMBus host controller. In
the tables the data addresses indicate 8 bits.The SMBus host controller should transmit 8 bits with
the most significant bit indicating which section of the EEPROM is to be addressed: the Processor
Information ROM (MSB = 0) or the Scratch EEPROM (MSB = 1).
6.4.4
SMBus Thermal Sensor
The Intel Xeon processor MP on the 0.13 micron process processor in INT-mPGA package provide
a SMBus thermal sensor as a means of acquiring thermal data from the processor. The thermal
sensor is composed of control logic, SMBus interface logic, a precision analog-to-digital converter,
and a precision current source. The sensor drives a small current through the p-n junction of a
thermal diode located on the processor core. The forward bias voltage generated across the thermal
diode is sensed and the precision A/D converter derives a single byte of thermal reference data, or
a “thermal byte reading.” The nominal precision of the least significant bit of a thermal byte is 1°C.
Table 36. Read Byte SMBus Packet
S
Slave
Address
Write
A
Command
Code
AS
Slave
Address
Rea
d
A
Data
///
P
17-bits
1
18-bits
11
7-bits
1
8-bits
1
Table 37. Write Byte SMBus Packet
S
Slave
Address
Write
A
Command Code
AData
AP
17-bits
1
18-bits
11