參數(shù)資料
型號(hào)： BX80526F1100128
廠(chǎng)商： INTEL CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 1100 MHz, MICROPROCESSOR, CPGA370
封裝： FLIP CHIP, PGA-370
文件頁(yè)數(shù)： 59/130頁(yè)
文件大?。?/td> 2654K
代理商： BX80526F1100128
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34
Datasheet
Intel Celeron Processor up to 1.10 GHz
2.12
System Bus AC Specifications
The Celeron processor system bus timings specified in this section are defined at the Intel Celeron
processor edge fingers and the processor core pins. Timings specified at the processor edge fingers
only apply to the S.E.P. Package and timings given at the processor core pins apply to all S.E.P.
Package and PGA packages. Unless otherwise specified, timings are tested at the processor core
during manufacturing. Timings at the processor edge fingers are specified by design
characterization. See Section 7.0 for the Intel Celeron processor signal definitions. Note that at
66 MHz system bus operation, the Intel Celeron processor timings at the processor edge
fingers are identical to the Pentium II processor timings at the edge fingers. See the Pentium
II Processor at 233, 266, 300, and 333 MHz (Order Number 243335) for more detail.
Table 9 through Table 26 list the AC specifications associated with the Intel Celeron processor
system bus. These specifications are broken into the following categories: Table 9 through Table 12
contain the system bus clock specifications, Table 13 and Table 14 contain the AGTL+
specifications, Table 17 and Table 18 are the CMOS signal group specifications, Table 20 contains
timings for the Reset conditions, Table 22 and Table 23 cover APIC bus timing, and Table 25 and
Table 26 cover TAP timing. For each pair of tables, the first table contains timing specifications for
measurement or simulation at the processor edge fingers. The second table contains specifications
for simulation at the processor core pads.
All Intel Celeron processor system bus AC specifications for the AGTL+ signal group are relative
to the rising edge of the BCLK input. All AGTL+ timings are referenced to VREF for both ‘0’ and
‘1’ logic levels unless otherwise specified.
The timings specified in this section should be used in conjunction with the I/O buffer models
provided by Intel. These I/O buffer models, which include package information, are available in
Quad format as the Intel Celeron
Processor I/O Buffer Models, Quad XTK Format (Electronic
Form). AGTL+ layout guidelines are also available in AP-585, Pentium II Processor AGTL+
Guidelines (Order Number 243330).
Care should be taken to read all notes associated with a particular timing parameter.
相關(guān)PDF資料
PDF描述
BU-61743F3-302W 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61743F3-362S 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61743F3-392L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-65171V1-140 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70
BU-61582F0-150 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70
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