參數(shù)資料
型號： BUK127-50GT
廠商： NXP SEMICONDUCTORS
元件分類： 外設及接口
英文描述： PowerMOS transistor Logic level TOPFET
中文描述： BUF OR INV BASED PRPHL DRVR, PDSO4
封裝： PLASTIC, SC-73, SOT-223, 4 PIN
文件頁數(shù)： 3/7頁
文件大?。?/td> 53K
代理商： BUK127-50GT
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK127-50GT
OUTPUT CHARACTERISTICS
Limits are for -40C
≤
T
mb
≤
150C; typicals are for T
mb
= 25 C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Off-state
V
IS
= 0 V
I
D
= 10 mA
I
D
= 200 mA; t
p
≤
300
μ
s;
δ
≤
0.01
V
DS
= 40 V
V
(CL)DSS
Drain-source clamping voltage
50
-
-
V
50
60
70
V
I
DSS
Drain source leakage current
-
-
-
100
10
μ
A
μ
A
T
mb
= 25 C
0.1
On-state
V
IS
≥
4 V; t
p
≤
300
μ
s;
δ
≤
0.01
I
D
= 100 mA
R
DS(ON)
Drain-source resistance
-
-
-
380
200
m
m
T
mb
= 25 C
150
INPUT CHARACTERISTICS
The supply for the logic and overload protection is taken from the input.
Limits are for -40C
≤
T
mb
≤
150C; typicals are for T
mb
= 25C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
IS(TO)
Input threshold voltage
V
DS
= 5 V; I
D
= 1 mA
0.6
1.1
-
2.4
2.1
V
V
T
mb
= 25C
V
IS
= 5 V
V
IS
= 4 V
V
IS
= 5 V
V
IS
= 3 V
1.6
I
IS
Input supply current
normal operation;
100
80
220
195
400
330
μ
A
μ
A
I
ISL
Input supply current
protection latched;
1.4
0.7
2
2.5
1.5
mA
mA
1.1
V
ISR
t
lr
V
(CL)IS
R
IG
Protection reset voltage
1
reset time t
r
≥
100
μ
s
V
IS1
= 5 V, V
IS2
< 1 V
I
I
= 1.5 mA
1.5
2
2.5
V
Latch reset time
10
40
100
μ
s
Input clamping voltage
5.5
-
8.5
V
Input series resistance
2
to gate of power MOSFET
T
mb
= 25C
-
2.5
-
k
OVERLOAD PROTECTION CHARACTERISTICS
TOPFET switches off to protect itself when one of the overload thresholds is exceeded. It remains latched off until
reset by the input.
SYMBOL
PARAMETER
CONDITIONS
Overload protection
V
IS
= 4 V to 5.5 V
I
D(TO)
Drain current trip threshold
T
j
= 25C
MIN.
TYP.
MAX.
UNIT
4
-
8
A
-40C
≤
T
j
≤
150C
3
-
9
A
Overtemperature protection
Threshold junction temperature V
IS
= 4 V to 5.5 V
T
j(TO)
150
170
-
C
1
The input voltage below which the overload protection circuits will be reset.
2
Not directly measureable from device terminals.
December 2001
3
Rev 2.000
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