參數(shù)資料
型號(hào)： BUF16820AIDAPRG4
英文描述： 14-Channel GAMMA VOLTAGE GENERATOR with Programmable VCOM Outputs and OTP Memory
中文描述： 14通道伽瑪電壓發(fā)生器具有可編程威科姆輸出和OTP存儲(chǔ)器
文件頁數(shù)： 9/30頁
文件大?。?/td> 681K
代理商： BUF16820AIDAPRG4
"#$%&'(
SBOS356A FEBRUARY 2006 REVISED OCTOBER 2006
www.ti.com
9
additional data are sent. The process continues until all
desired registers have been updated or a STOP condition
is sent.
To write to multiple DAC registers:
1.
Send a START condition on the bus.
2.
Send the device address and read/write bit = LOW.
The BUF16820 will acknowledge this byte.
3.
Send either the DAC_1 address byte to start at the first
DAC, or send the address byte for whichever DAC will
be the first in the sequence of DACs to be updated.
The BUF16820 will begin with this DAC and step
through subsequent DACs in sequential order.
4.
Send the bytes of data. Begin by sending the most
significant byte (bits D15D8, of which only bits D9
and D8 have meaning, and bits D15D14 must not be
01), followed by the least significant byte (bits D7D0).
The first two bytes are for the DAC addressed in step
3. Its register is automatically updated after receiving
the second byte. The next two bytes are for the
following DAC; that DAC register is updated after
receiving the fourth byte. This process continues until
the registers of all following DACs have been updated.
The BUF16820 will continue to accept data for a total
of 20 DACs; however, the four data sets following the
14th data set will be meaningless. The 19th and 20th
data sets will apply to V
COM1
and V
COM2
. The write
disable bit cannot be accessed using this method. It
must be written to using the
write to a single DAC
register
procedure.
5.
Send a STOP condition on the bus.
The BUF16820 acknowledges each byte. To terminate
communication, send a STOP or START condition on the
bus. Only DAC registers that have received both bytes of
data will be updated.
Reading:
Reading a DAC register returns the data stored in the
DAC. This data can differ from the data stored in the DAC
register; see the
Output Latch
section.
To read the DAC value:
1.
Send a START condition on the bus.
2.
Send the device address and read/write bit = LOW.
The BUF16820 will acknowledge this byte.
3.
Send the DAC address byte. Bits D7D5 must be set
to 0; Bits D4D0 are the DAC address.
Only
addresses 00000 to 01101, 10010, 10011, and
10100 are valid and will be acknowledged.
For
address 10100, only D0 has meaning. This bit is the
write disable bit.
4.
5.
Send a START or STOP/START condition.
Send correct device address and read/write
bit = HIGH. The BUF16820 will acknowledge this
byte.
Receive two bytes of data. They are for the specified
DAC. The first received byte is the most significant
byte (bits D15D8; only bits D9 and D8 have
meaning), and the next byte is the least significant
byte (bits D7D0).
Acknowledge after receiving the first byte.
Send a STOP condition on the bus or do not
acknowledge the second byte to end the read
transaction.
6.
7.
8.
Communication may be terminated by sending a
premature STOP or START condition on the bus, or by not
sending the acknowledge.
To Read Multiple DACs:
1.
Send a START condition on the bus.
2.
Send the device address and read/write bit = LOW.
The BUF16820 will acknowledge this byte.
3.
Send either the DAC_1 address byte to start at the first
DAC, or send the address byte for whichever DAC will
be the first in the sequence of DACs to be read. The
BUF16820 will begin with this DAC and step through
subsequent DACs in sequential order. The BUF16820
will continue to accept data for a total of 20 DACs;
however, the four data sets following the 14th data set
will be meaningless. The 19th and 20th data sets will
apply to V
COM1
and V
COM2
.
4.
Send a START or STOP/START condition on the bus.
5.
Send correct device address and read/write
bit = HIGH. The BUF16820 will acknowledge this
byte.
6.
Receive two bytes of data. They are for the specified
DAC. The first received byte is the most significant
byte (bits D15D8; only bits D9 and D8 have
meaning), and the next byte is the least significant
byte (bits D7D0).
7.
Acknowledge after receiving each byte.
8.
When all desired DACs have been read, send a STOP
or START condition on the bus.
Communication may be terminated by sending a
premature STOP or START condition on the bus, or by not
sending the acknowledge.
相關(guān)PDF資料
PDF描述
BUF20800 18-Channel GAMMA VOLTAGE GENERATOR with Two Programmable VCOM Channels
BUF20800AIDCPR 18-Channel GAMMA VOLTAGE GENERATOR with Two Programmable VCOM Channels
BUF20820 18-Channel GAMMA VOLTAGE GENERATOR with Two Programmable VCOM Channels
BUF20820AIDCPR 18-Channel GAMMA VOLTAGE GENERATOR with Two Programmable VCOM Channels
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