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參數(shù)資料
| 型號： | BU61586S3-102 |
| 英文描述： | MIL-STD-1553/ARINC Bus Controller/RTU |
| 中文描述： | MIL-STD-1553/ARINC總線控制器/ RTU通訊 |
| 文件頁數(shù)： | 14/32頁 |
| 文件大小： | 833K |
| 代理商： | BU61586S3-102 |
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14
Data Device Corporation
www.ddc-web.com
BU-61559 Series
C-12/02-300
In RT mode, the host processor may determine that a message
has been processed either by means of interrupts or by polling
the Interrupt Status Register or the Stack Pointer.
The Stack Pointer increments by four (modulo 256) during the
Start-of-Message sequence for each message processed. After
processing a message, the host CPU should read the Block
Status Word, Time Tag, data block starting address, and
Command Word received from the Message Block Descriptor in
the Stack. Assuming a valid message was received, it may then
read the received data from the respective data block.
The BU-61559 offers a great deal of flexibility in terms of RT
interrupt processing. In some systems, the transmission or
reception of a message with a particular subaddress denotes the
end of a complete set of consistent data. In this instance, the
user should use the RT SUBADDRESS CONTROL WORD
INTERRUPT in order to issue an interrupt request
only for a
particular T/R-subaddress
, rather than following every mes-
sage. One technique would then be for the host processor to
switch the active area of shared RAM, by toggling bit 13 of
Configuration Register #1 at this time.This allows the next group
of messages comprising a consistent data set to be stored in the
alternate area of the shared RAM address space.
IMPLEMENTING BULK DATA TRANSFERS
In systems involving bulk data transfers over the 1553 bus
to/from the same subaddress, the host CPU should set the
OVERWRITE INVALID DATA bit (bit 11) of Configuration
Register #2 and enable the RT CIRCULAR BUFFER
ROLLOVER interrupt request.By doing so, the routine transfer of
multiple messages to the selected subaddress,
including errors
and retries
, is transparent to the host processor.The BU-61559
will issue an interrupt request only after it has received the antic-
ipated number of
valid
data words to the particular subaddress.
The anticipated number of words to be received (or transmitted)
is programmable up to 8192 words.
RT COMMAND ILLEGALIZATION
The BU-61559 provides an internal mechanism for RT
Command Word illegalizing. The scheme utilizes a 256-word
area in the BU-61559's internal dual port RAM. A benefit of this
feature is reduced printed circuit board space requirements, by
eliminating the need for an external PROM, PLD, or RAM device
to perform the illegalizing function.The BU-61559's illegalization
scheme provides the maximum in flexibility, allowing any subset
of the 4096 possible combinations of broadcast/own address,
T/R bit, subaddress, and word count/mode code to be illegalized.
Another advantage of the RAM-based illegalization scheme is
that it is inherently self-testable.
In order to use the BU-61559's internal dual port RAM for RT
command illegalizing, it is necessary to connect the input signal
ILLENA to logic 1. By so doing, address locations 0300 through
03FF are dedicated for the message illegalizing function and
must not
be used for Stack or Data Block storage.The RT com-
mand illegalization option may be disabled by connecting
ILLENA to logic 0. In this instance, the BU-61559 assumes all
received Command Words are legal. If ILLENA is connected to
logic 0, address locations 0300 through 03FF may be used for
the storage of Stacks or Data Blocks.
It should be noted that the state of the ILLENA input has
no
effect
for BC or Monitor (MT) modes.
If the command illegalizing feature is used, address locations
0300-03FF
must
be mapped to the respective locations in the
BU-61559's 8K X 16 of
internal
shared RAM.
ADDRESSING THE ILLEGALIZATION TABLE
The addressing scheme of the illegalization RAM is illustrated by
FIGURE 16.As shown, the base address of the illegalizing RAM is
0300 (hex). The index into the illegalizing RAM is formulated by
means of BROADCAST/OWN ADDRESS, T/R bit, Subaddress,
and the MSB of the Word Count/Mode Code field (WC/MC4).
The internal RAM has 256 words reserved for command illegal-
ization. Broadcast commands may be illegalized separately from
non-broadcast receive commands and mode commands.
Commands may be illegalized down to the word count level. For
example, a one-word receive command to subaddress 1 may be
legal, while a 2-word receive command to subaddress 1 may be
illegalized.
The first 64 words of the Illegalization Table refer to broadcast
receive commands (two words per subaddress). The next 64
words refer to broadcast transmit commands. Since non-mode
code broadcast transmit commands are by definition invalid, this
section of the table (except for subaddresses 0 and 31) does
not
need to be initialized by the user.The next 64 words correspond
to non-broadcast receive commands.The final 64 words refer to
non-broadcast transmit commands. Messages with Word Count/
Mode Code (WC/MC) fields between 0 and 15 may be illegalized
by setting the corresponding data bits for the respective even-
numbered address locations in the illegalization table. Likewise,
messages with WC/MC fields between 16 and 31 may be illegal-
ized by setting the corresponding data bits for the respective
odd-numbered address locations in the illegalization table.
The following should be noted with regards to command illegal-
ization:
(1) To illegalize a particular word count for a given broadcast/own
address-T/R subaddress, the appropriate bit position in the
respective illegalization word should be set to logic 1. A bit
value of logic 0 designates the respective Command Word as
a legal command. The BU-61559 will respond to an illegal-
ized non-broadcast command with the Message Error bit set
in its RT Status Word.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BU61586S3-112 | MIL-STD-1553/ARINC Bus Controller/RTU |
| BU61586S3-122 | MIL-STD-1553/ARINC Bus Controller/RTU |
| BU61586S6-100 | MIL-STD-1553/ARINC Bus Controller/RTU |
| BU61586S6-110 | MIL-STD-1553/ARINC Bus Controller/RTU |
| BU61586S6-120 | MIL-STD-1553/ARINC Bus Controller/RTU |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BU61586V6-300 | 制造商:DDC 功能描述:MIL-STD-1553/ARINC BUS CONTROLLER/RTU, 70 Pin, Flat Pack |
| BU-61588 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MINIATURE ADVANCED COMMUNICATION ENGINE (MINI-ACE) AND MINI-ACE PLUS |
| BU-61588F0 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MINIATURE ADVANCED COMMUNICATION ENGINE (MINI-ACE) AND MINI-ACE PLUS |
| BU-61588F3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MINIATURE ADVANCED COMMUNICATION ENGINE (MINI-ACE) AND MINI-ACE PLUS |
| BU-61588F3-102 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553/ARINC Bus Controller/RTU |
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