- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369537 > BU61585S6-100 MIL-STD-1553/ARINC Bus Controller/RTU PDF資料下載
參數(shù)資料
| 型號： | BU61585S6-100 |
| 英文描述： | MIL-STD-1553/ARINC Bus Controller/RTU |
| 中文描述： | MIL-STD-1553/ARINC總線控制器/ RTU通訊 |
| 文件頁數(shù)： | 5/32頁 |
| 文件大小： | 833K |
| 代理商： | BU61585S6-100 |
第1頁第2頁第3頁第4頁當(dāng)前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
5
Data Device Corporation
www.ddc-web.com
BU-61559 Series
C-12/02-300
ADVANCED FEATURES
While maintaining functional and software compatibility to the
previous generation BUS-61553 series AIM-HY hybrids, the BU-
61559 incorporates a number of advanced features to support
1553B Notice 2. Other enhancements provided by the BU-61559
serve to provide the benefits of reduced board space require-
ments, expanded software flexibility, and reduced host processor
overhead.
INTERNAL TRI-STATE BUFFERS
The BU-61559 contains internal address latches and bidirection-
al data buffers to provide a direct interface to either a multiplexed
or a non-multiplexed processor bus.Alternatively, the latches and
buffers may be operated in a fully transparent mode to interface
to up to 64K words of external shared RAM and/or a component
set supporting the STANAG 3910 20 MHz data bus.
MEMORY MANAGEMENT
The BU-61559 incorporates complete memory management and
processor interface logic. The software interface to the host
processor is implemented by means of eight internal registers plus
a 64K word shared RAM address space, which generally includes
the 8K words of internal RAM.For all three modes, a stack area of
RAM is maintained. In BC mode, the stack allows for the schedul-
ing of multi-message frames. For all three modes, the stack pro-
vides a real time chronology of all messages processed. In addi-
tion to the stack processing, the memory management logic per-
forms storage, retrieval, and manipulation functions involving
pointer and message data structures for all three modes.
The BU-61559 provides a number of programmable options for
RT mode memory management. In compliance with MIL-STD-
1553B Notice 2, received data from broadcast messages may be
optionally separated from non-broadcast received data. For each
transmit, receive or broadcast subaddress, either a single-mes-
sage data block or a variable-sized (128 to 8192 words) circular
buffer may be allocated for data storage. In addition to helping
ensure data consistency, the circular buffer feature provides a
means of greatly reducing host processor overhead for bulk data
transfer applications. End-of-message interrupts may be enabled
either globally, following error messages on a Tx/Rx/Bcst-subad-
dress basis, or when any particular Tx/Rx/Bcst-subaddress circu-
lar buffer reaches its lower boundary. In addition to interrupts for
RT subaddress and circular buffer rollover conditions, the proces-
sor interface logic provides maskable interrupts and a 9-bit
Interrupt Status Register for end of message, end of BC message
list, erroneous messages, Status Set (BC mode), Time Tag
Register Rollover, and RT Address Parity Error conditions. The
Interrupt Status Register allows the host processor to determine
the cause of all interrupts by means of a single READ operation.
INTERNAL COMMAND ILLEGALIZATION
The BU-61559 implements internal command illegalization for
RT mode. The internal illegalization eliminates the need for an
external PROM, PLD, or RAM device.The illegalization architec-
ture allows for any subset of the 4096 possible combinations of
broadcast/own address, T/R bit, subaddress, and word
count/mode code to be illegalized. The BU-61559 illegalization
scheme is under software control of the host processor. As a
result, it is inherently self-testable.
INTERNAL TIME TAG
The BU-61559 includes an internal read/write Time Tag Register.
This register is a CPU read/write 16-bit counter with a program-
mable resolution of either 2, 4, 8, 16, 32, or 64 μs per LSB. The
Time Tag Register may also be clocked from an external oscilla-
tor. Another option allows the Time Tag Register to be incre-
mented under software control. This supports self-test for the
Time Tag Register.
For each message processed, the value of the Time Tag register
is loaded into the second location of the respective descriptor
stack entry (“TIME TAG WORD”) for both BC and RT modes.
Additional options are provided to clear the Time Tag Register
following a Synchronize (without data) mode command or load
the Time Tag Register following a Synchronize (with data) mode
command. Another option enables an interrupt request and a bit
in the Interrupt Status Register to be set when the Time Tag
Register rolls over from 0000 to FFFF. Assuming the Time Tag
Register is not loaded or reset, this will occur at approximately 4-
second time intervals for 64 μs/LSB resolution, down to 131 ms
intervals for 2 μs/LSB resolution.
Another programmable option for RT mode is for the Service
Request Status Word bit to be automatically cleared following the
BU-61559's response to a Transmit Vector Word mode command.
INTERFACE TO STANAG 3910 20 MHZ FIBER OPTIC BUS
For applications requiring a higher rate of data transfer than MIL-
STD-1553's 1 Mbps, it is possible to interface the BU-61559
directly to a component set supporting STANAG 3910. A
STANAG 3910 bus operates as an adjunct to, and is controlled
by, a MIL-STD-1553B Notice 2 (STANAG 3838) bus. The
STANAG 3910 standard defines a Manchester II encoded serial
data bus with a data rate of 20 Mbps, allowing for both electrical
and fiber optic implementations. STANAG 3910 is intended for
high-speed bulk data transfers, supporting message lengths of
up to 4096 words.
CLOCK INPUT
The BU-61559 requires an external 16 MHz clock input. All inter-
nal timing is derived from this clock. Refer to FIGURE 1 for the
short-term and long-term accuracy requirements of the input
clock frequency.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BU61585S6-110 | MIL-STD-1553/ARINC Bus Controller/RTU |
| BU61585S6-120 | MIL-STD-1553/ARINC Bus Controller/RTU |
| BU61585S6-200 | MIL-STD-1553/ARINC Bus Controller/RTU |
| BU61585S6-300 | MIL-STD-1553/ARINC Bus Controller/RTU |
| BU61585V1-100 | MIL-STD-1553/ARINC Bus Controller/RTU |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BU-61586 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |ACE |
| BU61586V6-300 | 制造商:DDC 功能描述:MIL-STD-1553/ARINC BUS CONTROLLER/RTU, 70 Pin, Flat Pack |
| BU-61588 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MINIATURE ADVANCED COMMUNICATION ENGINE (MINI-ACE) AND MINI-ACE PLUS |
| BU-61588F0 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MINIATURE ADVANCED COMMUNICATION ENGINE (MINI-ACE) AND MINI-ACE PLUS |
| BU-61588F3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MINIATURE ADVANCED COMMUNICATION ENGINE (MINI-ACE) AND MINI-ACE PLUS |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。