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參數(shù)資料
| 型號： | BU61585S1-300 |
| 英文描述： | MIL-STD-1553/ARINC Bus Controller/RTU |
| 中文描述： | MIL-STD-1553/ARINC總線控制器/ RTU通訊 |
| 文件頁數(shù)： | 17/32頁 |
| 文件大?。?/td> | 833K |
| 代理商： | BU61585S1-300 |
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17
Data Device Corporation
www.ddc-web.com
BU-61559 Series
C-12/02-300
address space.The first of the two words is the actual 16 bits of
data from the received word. The second word is the
Identification (ID) or “Tag” word.
The Monitor ID Word contains a Word Flag bit (always logic 1)
plus information relating to bus channel, word validity,
Command-Status/Data sync type, and inter-word gap time infor-
mation. This latter field includes a “Contiguous Data” bit as well
as an 8-bit gap time field, indicating 0 to 127 μs with a resolution
of 0.5 μs per LSB.
To take the BU-61559 monitor off-line, the host CPU must issue
a RESET command to the Start/Reset Register.
TABLE 6 illustrates a typical memory map for monitor mode.The
BU-61559 Identification Word is defined in FIGURE 17.
SELF-TEST
The BU-61559 contains a number of self-test features.The inter-
nal registers and shared RAM are accessible to the host proces-
sor at all times. The inclusion of wraparound capability for the
1553 front end transceiver and encoder/decoder supports BC
off-line and on-line self-test as well as RT on-line self-test.
The internal registers and shared RAM can be tested by means
of host processor software routines to implement “checker-
board”, “walking zero”, and “walking one” patterns and/or by writ-
ing the address as the data to each RAM location and then read-
ing back and verifying the contents of the entire RAM array.
A common element of all of the wraparound self-test features is
the method by which loopback words are checked. In each case,
the last word transmitted by the BC or RT is looped back into the
active Manchester II decoder. The received version of this word
is verified for: (1) Validity (sync field and Manchester II bit encod-
ing, bit count, and parity), and (2) A bit-by-bit comparison to the
transmitted version of the word.The loopback test is considered
to have failed if
either
of these two criteria is not met.
In the BC off-line self-test, the 1553 transmitter is inhibited, and
the encoder output is muxed directly into the respective decoder
input. For both the BC off-line and on-line self-tests, the received
version of the last transmitted word is stored in the next location
of the shared RAM following the transmitted loopback word. For
both the BC and RT loopback tests, the LOOPTEST FAIL bit in
the message's Block Status Word will be set as a result of a
failed loop test.
INTERFACE TO MIL-STD-1553 BUS
Interfacing the BU-61559 to a MIL-STD-1553 bus requires a pair
of BUS-25679 or BUS-29854 pulse transformers. These trans-
formers, or QPL equivalents, are available from Beta Transformer
Technology Corporation, a subsidiary of DDC. The BU-61559
hybrid and Beta Transformers may be wired for either direct cou-
pled or stub coupled configurations.
The interface between a BU-61559X1 or BU-61559X2 and a
MIL-STD-1553 bus is illustrated in FIGURE 18.
BUFFERED PROCESSOR INTERFACE
As a means of reducing printed circuit board space require-
ments, 16-bit address and data buffers are incorporated into the
BU-61559 AIM-HY'er.
As determined by the strapping of the input signal TRANSPAR-
ENT/BUFFERED, the BU-61559 processor interface may be
configured for either of two modes.TRANSPARENT/BUFFERED
should be strapped to logic “0” for buffered mode, logic “1” for
transparent mode.
Stack Pointer (Fixed Location)
0100
FFFF
0006
0004
Second Identification Word
0003
Second Received 1553 Word
0002
First Identification Word
0001
First Received 1553 Word
0000
ADDRESS (HEX)
FUNCTION
TABLE 6.TYPICAL MT MEMORY MAP
0005
FIGURE 17. MONITOR IDENTIFICATION WORD
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| BU61585S2-100 | MIL-STD-1553/ARINC Bus Controller/RTU |
| BU61585S2-110 | MIL-STD-1553/ARINC Bus Controller/RTU |
| BU61585S2-120 | MIL-STD-1553/ARINC Bus Controller/RTU |
| BU61585S2-200 | MIL-STD-1553/ARINC Bus Controller/RTU |
| BU61585S2-300 | MIL-STD-1553/ARINC Bus Controller/RTU |
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