
6
Data Device Corporation
www.ddc-web.com
BU-65743/65843/65863/65864
AC-6/11-0
One of the salient features of the PCI Mini-ACE Mark3 is its
Enhanced Bus Controller architecture. The Enhanced BC's
highly autonomous message sequence control engine provides
a means for offloading the host processor for implementing multi-
frame message scheduling, message retry schemes, data dou-
ble buffering, and asynchronous message insertion. For the
purpose of performing messaging to the host processor, the
Enhanced BC mode includes a General Purpose Queue, along
with user-defined interrupts.
The PCI Mini-ACE Mark3/Micro-ACE TE RT offers the same
choices of single and circular buffering for individual subad-
dresses as ACE, Mini-ACE(Plus), and Enhanced Mini-ACE. New
enhancements to the RT architecture include a global circular
buffering option for multiple (or all) receive subaddresses, a 50%
rollover interrupt for circular buffers, an interrupt status queue for
logging up to 32 interrupt events, and an option to automatically
initialize to RT mode with the Busy bit set. The interrupt status
queue and 50% rollover interrupt features are also included as
improvements to the PCI Mini-ACE Mark3/Micro-ACE TE's
Monitor architecture.
The PCI Mini-ACE Mark3 series terminals operate over the full
military temperature range of -55°C to +125°C.
Available
screened to MIL-PRF-38534C, the terminals are ideal for military
and industrial processor to 1553 applications.
The PCI Micro-ACE TE terminals operate over an extended tem-
perature range of -40°C to +100°C.
TRANSCEIVERS
The transceivers in the PCI Mini-ACE Mark3 series terminals are
fully monolithic, requiring only a +3.3V power input or a +5V
power input. The transmitters are voltage sources, which provide
improved line driving capability over current sources. This serves
to improve performance on long buses with many taps. The
transmitters also offer an option which satisfies the MIL-
STD-1760 requirement for a minimum of 20 volts peak-to-peak,
transformer coupled output. The transceivers in the PCI Micro-
ACE TE are only available with the MIL-STD-1760 option.
Besides eliminating the demand for an additional power supply,
the use of a +3.3V only or +5V only transceiver requires the use
of a step-up, rather than a step-down, isolation transformer. This
provides the advantage of higher terminal input impedance than
is possible for a 15 volt or 12 volt transmitter. As a result, there is
a greater margin for the input impedance test, mandated for the
INTRODUCTION
The BU-65743 RT, and BU-65843/65864 BC/RT/MT PCI Mini-
ACE Mark3/Micro-ACE TE family of MIL-STD-1553 terminals
comprise a complete integrated interface between a PCI host
processor and a MIL-STD-1553 bus.
All members of the PCI Mini-ACE Mark3 family are packaged in
the same 0.88" square, 80-lead CQFP package. All members of
the PCI Micro-ACE TE family are packaged in the same 0.8"
square, 324 ball, plastic BGA package.
The PCI Mini-ACE Mark3/Micro-ACE TE hybrid's provide soft-
ware compatibility with the Enhanced Mini-ACE, Mini-ACE (Plus)
terminals, as well as software compatibility with the older ACE
series.
The PCI Mini-ACE Mark3/Micro-ACE TE provides complete mul-
tiprotocol support of MIL-STD-1553A/B/McAir and STANAG
3838. All versions integrate dual transceivers; along with proto-
col, host interface, memory management logic; and a minimum
of 4K words of RAM. In addition, the BU-6586X BC/RT/MT ter-
minals include 64K words of internal RAM, with built-in parity
checking.
The PCI Mini-ACE Mark3s include a 3.3V or 5V voltage source
transceiver for improved line driving capability, with options for
MIL-STD-1760 and McAir compatibility. The PCI Micro-ACE TEs
are available with 3.3V or 5V voltage source transceivers but do
not offer a McAir option. Please consult the ordering information
section at the end of this document for all available options.
To provide further flexibility, the PCI Mini-ACE Mark3/Micro-ACE
TE has internal 1553 master clock dividers that allow operation
with either 10, 12, 16, or 20 MHz clock inputs. The 1553 master
clock divider is software programmable or, in the case of the
Micro ACE TE, can be controlled via pins when the RTBoot
mode is strapped.
The PCI Mini-ACE Mark3/Micro-ACE TEs are fully compliant
targets, as defined by the PCI Local Bus Specification Revision
2.2, using a 32 bit interface that operates at clock speeds of up
to 33 Mhz, from a 3.3V bus. The interface supports PCI interrupts
and contains a FIFO that handles PCI burst write transfer cycles.
The FIFO is deep enough to accept an entire 1553 message.
The PCI interface is NOT 5V tolerant and can not be used in a
5V PCI signaling environment.