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| 型號(hào)： | BU-65863F3-120 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80 |
| 封裝： | 0.880 INCH, CERAMIC, QFP-80 |
| 文件頁(yè)數(shù)： | 41/75頁(yè) |
| 文件大?。?/td> | 532K |
| 代理商： | BU-65863F3-120 |
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46
Data Device Corporation
www.ddc-web.com
BU-65743/65843/65863/65864
D-06/04-0
FIGURE 16. PCI READ OF ACE MEMORY/REGISTER
1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829
PCI memory read from ACE registers/memory with no DRR pending & FIFO empty
produces Retry & enques DRR. Master should attempt read as soon as possible
(preferably within 33 clocks). 3rd read produces disconnect with data, DRR complete
A
DAT
6h
0ns
250ns
500ns
750ns
I
PCICLK
IO
AD[31:0]
I
C/BE[3:0]#
I
FRAME#
I
IRDY#
O
TRDY#
O
STOP#
O
DEVSEL#
ACE MEMORY
(BAR0), DOUBLE
WORD
TYPE OF READ
TABLE 63. MIN/MAX DELAYED READ FORMULAS
ACE MEMORY
(BAR0), SINGLE
WORD OR ACE
REGISTER
(BAR1, DOUBLE
WORD OR
LOWER WORD
No CBEN#
ASSERTED OR
ACE REGISTER
(BAR1) UPPER
WORD
13 x PCI_CLK PERIOD
+ 11 x ACE_CLK
PERIOD
MIN TIME FORMULA
8 x PCI_CLK PERIOD
+ 5 x ACE_CLK
PERIOD
3 x PCI_CLK PERIOD
MAX TIME FORMULA
16 x PCI_CLK PERIOD
+ 14 x ACE_CLK
PERIOD
10 x PCI_CLK PERIOD
+ 6 x ACE_CLK PERIOD
3 x PCI_CLK PERIOD
The third case returns all zeroes and is shown only for com-
pleteness.
The following examples have the same conditions: PCI clock =
33MHz, ACE clock = 16MHz, no ACE contention.
Single word read
Min time = 8 x 30 nS + 5 x 62.5 nS = 552.5 nS
Max time = 10 x 30nS + 6 x 62.5 nS = 675 nS
Double word read
Min time = 13 x 30 nS + 11 x 62.5 nS = 1077.5 nS
Max time = 16 x 30nS + 14 x 62.5 nS = 1167.5 nS
In addition, the following amount of ACE clocks should be added
for maximum time if the ACE is active.
ENHANCED CPU ACCESS ENABLED,
SINGLE WORD XFER
ACE OPERATING MODE
TABLE 64. ADDITIONAL DRR DELAY FOR
CONTESTED ACE RAM ACCESS
MAXIMUM ADDITIONAL
ACE CLOCKS
3
ENHANCED CPU ACCESS ENABLED,
DOUBLE WORD XFER
6
ENHANCED CPU ACCESS DISABLED,
SINGLE WORD XFER
67
ENHANCED CPU ACCESS DISABLED,
DOUBLE WORD XFER
74
THE ENHANCED CPU ACCESS IC CONTROLLED BY BIT 14 OF CON-
FIGURATION REGISTER #6
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