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參數(shù)資料
| 型號(hào)： | BU-65179F3-110Z |
| 廠商： | DATA DEVICE CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 1 INCH, CERAMIC, QFP-72 |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 141K |
| 代理商： | BU-65179F3-110Z |
2
Data Device Corporation
www.ddc-web.com
BU-65178/65179*/61688*/61689*
F1 web-09/02-0
W
V
mA
s
5.5
5.25
100
200
350
500
800
200
300
450
600
900
19.5
23.5
51.5
131
7
2.5
9.5
18.5
22.5
50.5
129.5
668
4.5
4.75
17.5
21.5
49.5
127
4
1553 MESSAGE TIMING
Completion of CPU Write (BC Start)-
to-Start of Next Message
BC Intermessage Gap (Note 8)
BC/RT/MT Response Timeout
(Note 9)
! 18.5 nominal
! 22.5 nominal
! 50.5 nominal
! 128.0 nominal
RT Response Time (Note 11)
Transmitter Watchdog Timeout
UNITS
MAX
TYP
MIN
PARAMETER
0.475
0.905
1.160
1.670
0.200
0.630
0.885
1.395
0.5
1.00
1.43
1.86
1.0
1.50
1.93
2.36
3.22
0.25
0.68
1.11
1.97
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances
! BU-65178/61588X3
+5 V (Logic)
+5 V (Ch. A, Ch. B)
Current Drain (Total Hybrid)
! BU-65178/65179*/61588X0
+5 V (Logic)
! BU-65178/61588X3
+5 V (Logic, Ch. A, Ch. B)
Idle
25% Transmitter Duty Cycle
50% Transmitter Duty Cycle
100% Transmitter Duty Cycle
! BU-61688*/61689X0*
+5 V (Logic)
! BU-61688*/61689X3*
+5 V (Logic, Ch. A, Ch. B)
Idle
25% Transmitter Duty Cycle
50% Transmitter Duty Cycle
100% Transmitter Duty Cycle
5.0
95
245
360
590
POWER DISSIPATION
Total Hybrid
! BU-65178/65179*/61588X0
+5 V (Logic)
! BU-65178/61588X3/65179X3
Idle
25% Duty Cycle
50% Duty Cycle
100% Duty Cycle
! BU-61688*/61689X0*
+5 V (Logic)
! BU-61688*/61689X3*
Idle
25% Duty Cycle
50% Duty Cycle
100% Duty Cycle
Hottest Die
! BU-65178/61588X3/65179X3*/
BU-61688*/61689X3*
Idle
25% Duty Cycle
50% Duty Cycle
100% Duty Cycle
* Mini-ACE PLUS with 64K Words of RAM. RAM impact to Power
Supply is based on Host Processor activity; subtract 140 mA if Host
is idle.
V
A
V
mA
pF
0.8
10
-84
-42
-100
-50
0.4
-6.4
-3.2
50
2.0
-10
-692
-346
-794
-397
2.4
6.4
3.2
LOGIC
VIH
VIL
IIH (Vcc = 5.5 V, VIN = Vcc)
IIH (Vcc = 5.5 V, VIN = 2.7 V)
! SSFLAG/EXT_TRIG
! All Other Inputs
IIL (Vcc = 5.5 V, VIN = 0.4 V)
! SSFLAG/EXT_TRIG
! All Other Inputs
VOH (Vcc = 4.5 V, VIH = 2.7 V,
VIL = 0.2 V, IOH = max)
VOL (Vcc = 4.5 V, VIH = 2.7 V,
VIL = 0.2 V, IOL = max)
IOL
! DB15-DB0
A15-A0
MEMOE/ADDR_LAT
MEMWR/ZEROWAIT
DTREQ/16/8
DTACK/POLARITY_SEL
! INT
READYD
IOEN
IOH
! DB15-DB0
A15-A0
MEMOE/ADDR_LAT
MEMWR/ZEROWAIT
DTREQ/16/8
DTACK/POLARITY_SEL
! INT
READYD
IOEN
CI (Input Capacitance)
CIO (Bi-directional signal input
capacitance)
Vp-p
mVp-p,
diff
mV
nsec
9
27
10
250
300
7
21
22
150
6
18
20
-250
100
kohm
pF
Vp-p
Vpeak
5
0.860
10
2.5
0.20
0
V
6.0
7.0
Vcc+0.3
-0.3
ABSOLUTE MAXIMUM RATING
Supply Voltage
! Logic +5 V
! Transceiver +5 V (Note 12)
Logic
! Voltage Input Range
TABLE 1. BU-65178/65179*/61588/61688*/61689* SPECIFICATIONS
UNITS
MAX
TYP
MIN
PARAMETER
RECEIVER
Differential Input Resistance
(Notes 1-7)
Differential Input Capacitance
(Notes 1-7)
Threshold Voltage, Transformer
Coupled, Measured on Stub
Common Mode Voltage (Note 7)
TRANSMITTER
Differential Output Voltage
! Direct Coupled Across 35
,
Measured on Bus
! Transformer Coupled Across
70
, Measured on Bus:
Standard Product = – XX0
1760 Amplitude Compliant
Product = – XX2
( Note 13 and Ordering
Information – Test Criteria)
Output Noise, Differential (Direct
Coupled)
Output Offset Voltage, Transformer
Coupled Across 70 ohms
Rise/Fall Time
TABLE 1. BU-65178/65179*/61588/61688*/61689*SPECIFICATIONS (cont’d)
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