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參數(shù)資料
| 型號： | BU-65178P3-102 |
| 英文描述： | MIL-STD-1553/ARINC Bus Controller/RTU |
| 中文描述： | MIL-STD-1553/ARINC總線控制器/ RTU通訊 |
| 文件頁數(shù)： | 19/32頁 |
| 文件大?。?/td> | 833K |
| 代理商： | BU-65178P3-102 |
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19
Data Device Corporation
www.ddc-web.com
BU-61559 Series
C-12/02-300
FIGURE 19. BU-61559 INTERCONNECTION DIAGRAM FOR BUFFERED MODE
the CPU reading internal RAM (or registers), for 1553 write
accesses, for 1553 read accesses from internal RAM, and for
internal transfers of received Command Words in RT mode.The
data buffers are directed inward (toward the memory data bus)
for CPU write accesses to internal RAM (or registers) or for the
1553 reading external RAM.
It should be noted that A15 through A0 as well as D15 through
D0 have internal pullup resistors to +5V. External pullup resistors
are not required
.
FIGURE 19 illustrates a generic interconnection of the BU-61559
in the buffered mode. In this configuration, only the 8K words of
internal RAM are used. No external address or data buffers are
required.
FIGURE 20 illustrates a generic interconnection of the BU-61559
in the transparent mode. This configuration supports up to 64k
words of address space. This may optionally include the 8K
words of internal RAM. In this configuration, external address
and data buffers
are required
.
BU-61559
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| BU-65178P3-112 | MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-65178P3-122 | MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-65179F3-102 | MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-65179F3-112 | MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-65179F3-122 | MIL-STD-1553/ARINC Bus Controller/RTU |
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