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| 型號(hào)： | BU-65171V3-172L |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70 |
| 封裝： | 1.900 X 1 INCH, 0.150 INCH HEIGHT, LOW PROFILE, CERAMIC, FP-70 |
| 文件頁(yè)數(shù)： | 15/44頁(yè) |
| 文件大小： | 298K |
| 代理商： | BU-65171V3-172L |
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22
FIGURE 9. 16-BIT BUFFERED MODE
HOST
ACE
55
55
8
7
5
4
1
2
3
CH. A
TX/RXA
55
55
8
7
5
4
1
2
3
CH. B
TX/RXB
RTAD4-RTAD0
RT
ADDRESS,
PARITY
RTADP
D15-D0
+5V
+15V
CLK IN
16 MHz
CLOCK
OSCILLATOR
N/C
POLARITY_SEL
(NOTE 2)
ZERO_WAIT
(NOTE 3)
ADDRESS
DECODER
SELECT
MEM/REG
RD/WR
STRBD
READYD
TAG_CLK
RD/WR
CPU STROBE
CPU ACKNOWLEDGE
(NOTE 4)
RESET
NOTES:
+5V
MSTCLR
SSFLAG/EXT_TRIG
INT
CPU INTERRUPT REQUEST
3. ZERO_WAIT SHOULD BE STRAPPED TO
LOGIC "1" FOR NON-ZERO WAIT INTERFACE
AND TO LOGIC "0" FOR ZERO WAIT INTERFACE.
4. CPU ACKNOWLEDGE PROCESSOR INPUT ONLY
FOR NON-ZERO WAIT TYPE OF INTERFACE.
1. CPU ADDRESS LATCH SIGNAL PROVIDED BY
PROCESSORS WITH MULTIPLEXED ADDRESS/DATA
BUSES.
2. IF POLARITY_SEL = "1", RD/WR IS HIGH TO READ,
LOW TO WRITE.
IF POLARITY_SEL = "0", RD/WR IS LOW TO READ,
HIGH TO WRITE.
A15-A12
A11-A0
N/C
ADDR_LAT
TRANSPARENT/BUFFERED
CPU ADDRESS LATCH (NOTE 1)
+5V
16/8_BIT
TRIGGER_SEL
MSB/LSB
+5V
* Additional address lines A12 and A13 are required with the BU-61585.
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