- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369545 > BU-65170V2-300 MIL-STD-1553/ARINC Bus Controller/RTU PDF資料下載
參數(shù)資料
| 型號： | BU-65170V2-300 |
| 英文描述： | MIL-STD-1553/ARINC Bus Controller/RTU |
| 中文描述： | MIL-STD-1553/ARINC總線控制器/ RTU通訊 |
| 文件頁數(shù)： | 24/32頁 |
| 文件大?。?/td> | 833K |
| 代理商： | BU-65170V2-300 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
24
Data Device Corporation
www.ddc-web.com
BU-61559 Series
C-12/02-300
FIGURE 23. CPU WRITING RAM (SHOWN FOR BUFFERED MODE)
Notes for FIGURE 23:
1. For the 16-bit buffered nonzero wait configuration TRANSPARENT/BUFFERED must be connected to logic "0". ZERO_WAIT* and DTREQ/16/8 must be connected to logic "1".The inputs TRIG-
GER_SEL and MSB/LSB may be connected to either +5V or ground.
2. SELECT and STRBD may be tied together. IOEN goes low on the first rising CLK edge when SELECT STRBD is sampled low (satisfying t1) and the BU-61559's protocol/memory management
logic is not accessing the internal RAM. When this occurs, IOEN goes low, starting the transfer cycle. After IOEN goes low, SELECT may be released high.
3. MEM/REG must be presented high for memory access, low for register access.
4. MEM/REG and RD/WR are buffered transparently until the first falling edge of CLK after IOEN goes low. After this CLK edge, MEM/REG and RD/WR become latched internally.
5.The logic sense for RD/WR in the diagram assumes that POLARITY_SEL is connected to logic "1". If POLARITY_SEL is connected to logic "0", RD/WR must be asserted high to write.
6.The timing for IOEN and READYD outputs assumes a 50 pf load. For loading above 50 pf, the validity of IOEN and READYD is delayed by an additional 0.14 ns/pf typ, 0.28 ns/pf max.
7.Timing for A15-A0, MEM/REG, and SELECT assumes ADDR-LAT is connected to logic "1". Refer to Address Latch timing for additional details.
8. Internal RAM is accessed by A11 through A0 (A13 through A0 for 61585, 61586, 61582, and 61583 and A15 through A0 for 61688 and 61689). Registers are accessed by A4 through A0.
9.The address bus A15-A0 and data bus D15-D0 are internally buffered transparently until the first rising edge of CLK after IOEN goes low. After this CLK edge, A15-A0 and D15-D0 become latched
internally.
10. Setup time given for use in worst case timing calculations. None of the input signals are required to be synchronized to the system clock. When SELECT and STRBD do not meet the setup time
of t1, but occur during the setup time of an internal flip-flop, an additional clock cycle will be inserted between the falling clock edge that latches MEM/REG and RD/WR and the rising clock edge that
latches the address (A15-A0) and data (D15-D0). When this occurs, the pulse width of IOEN falling to READYD falling (t14) increases by one clock cycle and the address and data hold time (t12+t13)
must be increased by one clock cycle.
t3
MEM/REG and RD/WR setup time following SELECT and STRBD low (Notes 3,4,5,7)
t2
107.5
2.8
ns
ns
30
ns
50
ns
10
ns
MIN
BU-61559
DESCRIPTION
REF
CPU WRITING RAM OR REGISTERS (SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE)
TYP MAX
UNIT
SELECT and STRBD low delay to IOEN low (uncontended access) (Notes 2,6)
SELECT and STRBD low delay to IOEN low (contended access) (Notes 2,6)
t1
10
ns
SELECT and STRBD low setup time prior to clock rising edge (Note 2,10)
t4
Address valid setup time following SELECT and STRBD low.
t5
Input Data Valid setup time following SELECT and STRBD low.
35
ns
10
ns
t6
CLOCK IN rising edge delay to IOEN falling edge (Note 6)
t7
SELECT hold time following IOEN falling (Note 2)
30
ns
30
ns
t8
MEM/REG, RD/WR setup time prior to CLOCK IN falling edge (Notes 3,4,5,7)
t9
MEM/REG, RD/WR hold time following CLOCK IN falling edge (Notes 3,4,5,7)
30
ns
10
ns
t10
Address valid setup time prior to CLOCK IN rising edge (Notes 7,8,9)
t11
Input Data valid setup time prior to CLOCK IN rising edge
30
ns
t12
Address valid hold time following CLOCK IN rising edge (Notes 7,8,9,10)
30
ns
170
187.5 205
ns
t13
Input Data valid hold time following CLOCK IN rising edge (Notes 9,10)
t14
IOEN falling delay to READYD falling (Notes 6,10)
35
∞
ns
ns
t15
CLOCK IN rising edge delay to READYD falling (Note 6)
t16
READYD falling to STRBD rising release time.
30
ns
t17
STRBD rising edge delay to IOEN rising edge and READYD rising edge (Note 6)
0
ns
t18
STRBD valid high hold time from READYD rising edge
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BU-65170V3-102 | MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-65170V3-112 | MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-65170V3-122 | MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-65170V6-100 | MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-65171G3-102 | MIL-STD-1553/ARINC Bus Controller/RTU |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BU65170V3100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| BU65170V3110 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| BU65170V3120 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| BU65170V3150 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| BU65170V3300 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。