參數(shù)資料
型號(hào)： BU-65142F2-580K
廠商： DATA DEVICE CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP78
封裝： CERAMIC, DFP-78
文件頁(yè)數(shù)： 14/26頁(yè)
文件大?。?/td> 247K
代理商： BU-65142F2-580K
21
Data Device Corporation
www.ddc-web.com
BU-65142 and BUS-65142 SERIES
U-05/02-0
Remote Terminal Flag--Input signal used to
control the terminal flag bit in the status regis-
ter. If LOW when the status word is updated,
the terminal flag bit would be set; if HIGH, it
would be cleared. Normally connected to
RTFAIL .
Multiplexed address line output. When
INCMD is LOW or A5 thru A9 are all
zeroes or all ones (Mode Command), it
represents the latched output of the 3rd
MSB in the word count field of the com-
mand word. When INCMD is HIGH and
A5 thru A9 are not all zeroes or all ones,
it represents the 3rd MSB of the current
word counter.
Input from the LOW side of the primary
side of the coupling transformer that
connects to the B channel of the 1553
Bus.
+5 V input power supply connection for
the B channel transceiver.
HIGH, output to the primary side of the
coupling transformer that connects to
the B channel transceiver.
Input of Address Parity Bit. The combi-
nation of assigned terminal address and
ADDRP must be odd parity for the RT to
work.
Input of the 2nd LSB of the assigned
terminal address.
Input of the 2nd MSB of the assigned
terminal address.
Power supply return for RTU digital logic
section.
+5V input power supply connection for
RTU digital logic section.
A2
(WC2/
CSW2)
RXDATA B
+5VB
-VB
TXDATA B
ADDRP
ADDRB
ADDRD
GND
+5V
80
39
37
35
33
31
29
27
25
23
Bi-directional parallel data bus Bit 14
DB14
21
Bi-directional parallel data bus Bit 12
DB12
19
Bi-directional parallel data bus Bit 10
DB10
17
Bi-directional parallel data bus Bit 8
DB8
15
Bi-directional parallel data bus Bit 6
DB6
13
Bi-directional parallel data bus Bit 4
DB4
11
Bi-directional parallel data bus Bit 2
DB2
9
Bi-directional parallel data bus Bit 0 (LSB)
DB0
7
Latched output of the 2nd LSB in the
subaddress field of the command word.
A6
(SA1)
5
Latched output of the 2nd MSB in the
subaddress field of the command word.
A8
(SA3)
3
New Bus Grant -- LOW level output
pulse (166ns) used to indicate the start
of a new protocol sequence in response
to the command word just received.
NBGT
43
HIGH output to the primary side of the
coupling transformer that connects to
the A channel of the 1553 Bus.
TXDATA A
45
-15V/-12V input power supply connec-
tion for the BUS-65142/43/44/45 and
BU-65142X1/2 A Channel transceiver
(No connection for BU-65142X3).
+5V input power supply connection for
the A channel transceiver.
-VA
+5VA
47
49
77
38
36
34
32
30
28
26
24
22
60
59
58
57
56
55
54
53
52
51
20
50
18
49
16
48
14
47
12
46
10
45
8
44
6
43
4
42
2
41
40
42
39
38
37
44
46
FUNCTION
78-
Pin
Flat-
Pack
DESCRIPTION
PACKAGE & PIN
82-
Pin
Flat-
Pack
TABLE 6. PIN FUNCTIONS (continued)
Watchdog Timeout test point--DO NOT USE.
(See note 3)* (input).
TEST
1
60
RTFLAG
62
Input resets entire RT when LOW.
RESET
64
Buffer Enable-- input used to enable or tri-state
the internal data bus buffers when they are dri-
ving the bus. When LOW, the data bus buffers
are enabled. Could be connected to DTACK, if
RT is sharing the same data bus as the
subsystem. (see note 2)*.
BUF ENA
66
16MHz Clock Input--input for the master
clock used to run RTU circuits.
16MHz
IN
68
GBR
70
RD/WR
72
Data Transfer Acknowledge-- active LOW out-
put signal during data transfers to or from the
subsystem indicating the RTU has received the
DTGRT in response to DTREQ and is present-
ly doing the transfer. Can be connected direct-
ly to (BUF ENA) for control of tri-state data
buffers; and to tri-state address buffer control
lines, if they are used.
DTACK
76
A4
(WC4/
CWC4)
74
57
70
63
71
59
69
61
68
63
67
65
66
67
65
69
64
62
73
FUNC-
TION
78-
Pin
Flat-
Pack
DESCRIPTION
PACKAGE & PIN
82-
Pin
Flat-
Pack
TABLE 6. PIN FUNCTIONS (continued)
78-
Pin
QIP
78-
Pin
QIP
Read/Write - output signal controls direction of
the internal data bus buffers (logic “1”= reading
data via D15-D0; logic “0” = writing data via
D15-D0). Prior to reception of a 1553 com-
mand word, RD/WR will be logic “0”,indicating
that the BU(S)-65142 is writing data to the con-
nected subsystem.Following the reception/
transfer of a transmit command word, RD/WR
transitions from low to high,remains high until
after the last data word is read from the system
for transmission on the 1553 bus.After that last
data word transfer,RD/WR returns to logic “0”.
Multiplexed address line output. When INCMD
is LOW or A5 thru A9 are all zeroes or all ones
(Mode Command), it represents the latched
output of the MSB in the word count field of the
command word. When INCMD is HIGH and
A5 thru A9 are not all zeroes or all ones, it rep-
resents the MSB of the current word counter.
Good Block Received--LOW level output pulse
(.5s) used to flag the subsystem that a valid,
legal, non-mode receive command with the
correct number of data words has been
received without a message error and success-
fully transferred to the subsystem.
A0
(WCO/
CSWO)
78
75
61
Multiplexed address line output. When INCMD
is LOW or A5 thru A9 are all zeroes or all ones
(Mode Command), it represents the latched
output of the LSB in the word count field of the
command word. When INCMD is HIGH and A5
thru A9 are not all zeroes or all ones, it repre-
sents the LSB of the current word counter.
-15V/-12V input power supply connec-
tion for the BUS-65142/43/44/45 and
BU-65142X1/2 B Channel transceiver
(No connection for BU-65142X3).
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