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參數(shù)資料
| 型號： | BU-65142D2-390K |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78 |
| 封裝： | CERAMIC, QIP-78 |
| 文件頁數(shù)： | 26/26頁 |
| 文件大?。?/td> | 247K |
| 代理商： | BU-65142D2-390K |
9
Data Device Corporation
www.ddc-web.com
BU-65142 and BUS-65142 SERIES
U-05/02-0
~ ~
~~
~ ~
15 1413 12 1110 9 8 7 6 5 4 3 2 1 0 P
DATA
DATA 15 14 1312 1110 9 8 7 6 5 4 3 2 1 0 P
200ns min
4.7±.3 max
1.1±.2s
300ns max
max
100-150ns
100ns max
225-275ns
475-550ns
50ns min
100ns max
300ns max
9.35s max
100-150ns
CURRENT WORD COUNT = 00010
CURRENT WORD COUNT = 00001
note 7
DTGRT
IS RECOGNIZED
DATA TRANSFER
STARTS, SUBSYSTEM
SHOULD BE DRIVING
THE DATA BUS
INTERNAL DATA
BUFFERS ARE NOW
INPUTS
1st DATA WORD
TRANSFER
INTERNAL DATA
BUFFERS ARE NOW
INPUTS
2nd DATA WORD
TRANSFER
SUBSYSTEM DATA
MUST BE VALID
50ns min
DTGRT
IS RECOGNIZED
DATA TRANSFER
STARTS, SUBSYSTEM
SHOULD BE DRIVING
THE DATA BUS
ENCODER REGISTERS
AVAILABLE FOR NEXT
WORD RTU
REQUESTS DATA BUS
FOR 2nd DATA WORD
TRANSFER
SUBSYSTEM DATA
MUST BE VALID
225-275ns
475-550ns
1. LEGEND
DON'T CARE
DATA BUS UNDEFINED
2. EACH WORD IS DRIVEN FOR
18-19S ON D15-D05.
IF BUF ENA IS ACTIVE THE LAST WORD IS AVAILABLE FOR 3.5-4S SINCE THE STATUS WORD MUST BE SUPPORTED.
3. DATA BUS IS SHOWN WITH BUF ENA CONNECTED TO DTACK (SEE PIN FUNCTION TABLE, PIN 67)
4. THE POSITION OF DTACK WILL VARY DEPENDING ON WHEN DTGRT IS ISSUED; THE TIME WILL BE 100nS MIN to 150ns MAX FROM DTGRT.
5. HSFAIL IS ASSERTED UPON EXCESS DTGRT RESPONSE TIME.
INCMD WILL SUBSEQUENTLY GO LOW, AND NO FURTHER DATA TRANSFERS WILL OCCUR.
6. RTFAIL IS CLEARED WHEN THE STATUS WORD IS TRANSMITTED. ONCE SET, FLAG WILL REMAIN SET FOR THE ENTIRE MESSAGE.
THE INCMD FALLING EDGE CAN BE USED TO LATCH RTFAIL STATUS.
7. 100nS MIN REPRESENTS SETUP TIME FOR VALID DATA BEFORE DTSTR GOES LOW FOR A WRITE CYCLE.
A READ CYCLE REQUIRES VALID DATA 160 nS MAX AFTER DTACK GOES LOW
NOTES
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