參數(shù)資料
型號： BU-65142D2-130W
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
封裝： CERAMIC, QIP-78
文件頁數(shù)： 3/26頁
文件大?。?/td> 247K
代理商： BU-65142D2-130W
11
Data Device Corporation
www.ddc-web.com
BU-65142 and BUS-65142 SERIES
U-05/02-0
~ ~
15 141312 1110 9 8 7 6 5 4 3 2 1 0 P
STATUS
4.7±.3 max
1.1±.2s
200ns min
300ns max
100-150ns
2.85s max
CURRENT WORD COUNT = 00001
CURRENT WORD COUNT = 00010
note 7
100ns max
4.5s
225-275ns
2nd DATA WORD
RECEIVED &
VALIDATED
RTU REQUESTS DATA
BUS FOR DATA WORD
TRANSFER
50ns min
RTU DATA VALID
475-550ns
2nd DATAWORD
TRANSFER
STATUS WORD
TRANSFERRED TO
ENCODER REGISTERS
DTGRT
IS RECOGNIZED
DATA TRANSFER
STARTS
NO MORE
CONTINUOUS DATA
ENCODER
STARTED UP
RT FAIL
IS CLEARED
IF IT WAS SET
1. LEGEND
DON'T CARE
DATA BUS UNDEFINED
REPRESENTS THE SEQUENCE OF EVENTS IF THE COMMAND WAS BROADCAST.
NOTE: NO STATUS WOULD BE TRANSMITTED ON 1553 BUS.
2. EACH WORD IS DRIVEN FOR
18-19S ON D15-D0.
IF BUF ENA IS ACTIVE THE LAST WORD IS AVAILABLE FOR 3.5-4S SINCE THE STATUS WORD MUST BE SUPPORTED.
3. DATA BUS IS SHOWN WITH BUF ENA CONNECTED TO DTACK (SEE PIN FUNCTION TABLE, PIN 67)
4. THE POSITION OF DTACK WILL VARY DEPENDING ON WHEN DTGRT IS ISSUED; THE TIME WILL BE 100ns MIN TO 150ns MAX FROM DTREQ
5. HSFAIL IS ASSERTED UPON EXCESS DTGRT RESPONSE TIME. GBR WILL NOT BE SET.
6. RTFAIL IS CLEARED WHEN THE STATUS WORD IS TRANSMITTED. ONCE SET, FLAG WILL REMAIN SET FOR THE ENTIRE MESSAGE.
THE INCMD FALLING EDGE CAN BE USED TO LATCH RTFAIL STATUS.
7. 100ns MIN REPRESENTS SETUP TIME FOR VALID DATA BEFORE DTSTR GOES LOW.
NOTES
相關(guān)PDF資料
PDF描述
BUS-65143-170Z 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, QIP78
BUS-65143-190K 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, QIP78
BUS-65145-150Z 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, DFP82
BUS-65145-170L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, DFP82
BU-61588F3-130Y 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
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