• 參數(shù)資料
      型號(hào): BU-65142D1-840S
      廠商: DATA DEVICE CORP
      元件分類: 微控制器/微處理器
      英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
      封裝: CERAMIC, QIP-78
      文件頁(yè)數(shù): 9/26頁(yè)
      文件大小: 247K
      代理商: BU-65142D1-840S
      17
      Data Device Corporation
      www.ddc-web.com
      BU-65142 and BUS-65142 SERIES
      U-05/02-0
      RESERVED MODE COMMAND (01001-01111)
      MESSAGE SEQUENCE = RESERVED MODE COMMAND * STATUS
      The RTU responds with clear status and no data. If the command is illegalized through an optional PROM, the message error bit is set and only
      the status word is transmitted.
      ERROR CONDITIONS
      1. Invalid Command. No response, command ignored.
      2. Command Followed by Data Word. No status response. Bits Set: message error (SW), High Word Count (BIT Word).
      3. T/R bit Set to Zero. No status response. Bits set: message error (S/W), Illegal Mode Code (BIT Word).
      4. Zero T/R bit and Broadcast Address. No status response. Bits Set: message error, broadcast received (S/W), Illegal Mode Code (BIT Word).
      RESET REMOTE TERMINAL (01000)
      MESSAGE SEQUENCE = RESET REMOTE TERMINAL * STATUS
      The RTU responds with status and internally resets. Transmitter shutdown, mode commands, BIT Word, and inhibit terminal flag commands will be
      reset. If the command was broadcast, the broadcast received bit is set and the status word is suppressed.
      ERROR CONDITIONS
      1. Invalid Command. No response, command ignored.
      2. Command Followed by Data Word. No status response. Bits Set: message error (SW), High Word Count (BIT Word).
      3. T/R bit Set to Zero. No status response. Bits Set: message error (S/W), T/R Error (BIT Word).
      4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (S/W), T/R Error (BIT Word).
      OVERRIDE INHIBIT TERMINAL FLAG BIT (00111)
      MESSAGE SEQUENCE = OVERRIDE INHIBIT TERMINAL FLAG * STATUS
      The RTU responds with status and reactivates the terminal flag bit in the status register. If the command was broadcast, the broadcast received bit
      is set and status transmission is suppressed.
      ERROR CONDITIONS
      1. Invalid Command. No response, command ignored.
      2. Command Followed by Data Word. No status response. Bits Set: message error (SW), High Word Count (BIT Word)
      3. T/R bit Set to Zero. No status response. Bits set: message error (S/W), T/R Error (BIT Word).
      4. Zero T/R bit and Broadcast Address. No status response. Bits Set: message error, broadcast received (S/W), T/R Error (BIT Word).
      INHIBIT TERMINAL FLAG BIT (00110)
      MESSAGE SEQUENCE = INHIBIT TERMINAL FLAG * STATUS
      The RTU responds with status and inhibits further internal or external setting of the terminal flag bit in the status register. Once the terminal flag
      has been inhibited, it can only be reactivated by an Override Inhibit Terminal Flag or Reset RT command. If the command was broadcast, the
      broadcast received bit is set and status transmission is suppressed.
      ERROR CONDITIONS
      1. Invalid Command. No response, command ignored.
      2. Command Followed by Data Word. No status response. Bits Set: message error (SW), High Word Count (BIT Word)
      3. T/R bit Set to Zero. No status response. Bits set: message error (S/W), T/R Error (BIT Word).
      4. Zero T/R bit and Broadcast Address. No status response. Bits Set: message error, broadcast received (S/W), T/R Error (BIT Word).
      OVERRIDE TRANSMITTER SHUTDOWN (00101)
      MESSAGE SEQUENCE = OVERRIDE SHUTDOWN * STATUS
      This command is only used with dual redundant bus systems. The RTU responds with status. At the end of the status transmission, the RTU re-
      enables the transmitter of the redundant bus. If the command was broadcast, the broadcast received bit is set and status transmission is sup-
      pressed.
      ERROR CONDITIONS
      1. Invalid Command. No response, command ignored.
      2. Command Followed by Data Word. No status response. Bits Set: message error (SW), High Word Count (BIT Word)
      3. T/R bit Set to Zero. No status response. Bits set: message error, broadcast received (S/W), T/R Error (BIT Word).
      4. Zero T/R bit and Broadcast Address. No status response. Bits Set: message error, broadcast received (S/W), Illegal Mode Code,
      T/R Error (BIT Word).
      TABLE 5. MODE CODES IMPLEMENTED (continued)
      * = Status Response Time
      相關(guān)PDF資料
      PDF描述
      BU-65142D2-200W 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
      BU-65142D2-430Q 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
      BU-65142D2-470L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
      BU-65142D2-480L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
      BU-65142D2-810L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
      相關(guān)代理商/技術(shù)參數(shù)
      參數(shù)描述
      BU65170G0-100 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC
      BU65170G0-110 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC
      BU65170G0-120 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC
      BU65170G0-200 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC
      BU65170G0-300 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC