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Data Device Corporation
www.ddc-web.com
BU-65142 SERIES
V-01/03-0
TABLE 1. BU-65142 SPECIFICATIONS (continued)
UNITS
MAX
TYP
MIN
PARAMETER
°C/W
°C
20
150
125
150
+300
-55
-65
THERMAL
Thermal Resistance, Junction-to-
Case, Hottest Die (
θJC)
Operating Junction Temperature
Storage Temperature
Lead Temperature
(soldering, 10 sec.)
in
(mm)
in
(mm)
in
(mm)
PHYSICAL CHARACTERISTICS
Size
78-pin Ceramic QIP (BU-65142D)
78-pin Ceramic Flat Pack
(BU-65142F)
Weight
1.80 x 2.10 x 0.21
(45.7 x 53.3 x 5.3)
1.80 x 2.10 x 0.21
(45.7 x 53.3 x 5.3)
1.7
(48.2)
Note (for TABLE 1):
Power dissipation specifications assume a transformer coupled
configuration, with external dissipation (while transmitting) of
0.14 watts for the active isolation transformer, 0.08 watts for the
active coupling transformer, 0.45 watts for each of the two bus
isolation resistors, and 0.15 watts for each of the two bus termi-
nation resistors.
QCI TESTING
MIL-STD-883, Method 1018
MIL-STD-883, Method 1010 Condition C
and MIL-STD-883, Method 2012
MIL-STD-883, Method 2012
MIL-STD-883, Method 2023
MIL-STD-883, Method 1015
MIL-STD-883, Method 2020 Condition A
METHOD
Moisture Content Limit of
5000 PPM
Extended Temperature
Cycling:
20 Cycles Including
Radiographic (X-Ray)
Testing
Radiographic (X-Ray)
Analysis
100% Non-Destructive
Wirebond Pull
320-Hour Burn-In
Particle Impact Noise
Detection (PIND)
ASSEMBLY & TEST
ELEMENT EVALUATION
TABLE 3. HIGH RELIABILITY SCREENING OPTIONS
TABLE 2. BU-65142 SERIES RADIATION SPECIFICATIONS
PART
NUMBER
TOTAL
DOSE
SINGLE EVENT
UPSET
SINGLE EVENT
LATCHUP
BU-65142
X1/X2
300K
Rad
5.3 x 10-6
errors/device-day,
(LET Threshold of
59 MeV/mg/cm2)
Immune
BU-65142
X3
175K
Rad
5.3 x 10-6
errors/device-day,
(LET Threshold of
59 MeV/mg/cm2)
Immune
MIL-STD-883, Method 2018
MIL-STD-883, Method 2010 Condition A
MIL-STD-750, Method 2072 and 2073
MIL-STD-883, Method 2032 Class S
METHOD
SEM Analysis for Integrated
Circuits
Visual Inspection:
Integrated Circuits
Transistors & Diodes
Passive Components
ELEMENT EVALUATION
TABLE 3. HIGH RELIABILITY SCREENING OPTIONS
HIGH-REL SCREENING
DDC is committed to the design and manufacture of hybrids and
transformers with enhanced processing and screening for
spaceborne applications and other systems requiring the high-
est levels of reliability. These platforms include launch vehicles,
satellites and the International Space Station.
DDC has tailored its design methodologies to optimize the fabri-
cation of space level hybrids. The intent of the design guidelines
is to minimize the number of die and wirebonds, minimize the
number of substrate layers, and maximize the space between
components. DDC’s space grade products combine analog bipo-
lar and rad hard CMOS technology to provide various levels of
radiation tolerance.
The BU-65142 is packaged in a 78-pin ceramic package. In con-
trast to Kovar (metal) packages, the use of ceramic eliminates
the hermeticity problems associated with the glass beads used
in the metal packages. In addition, ceramic packages provide
more rigid leads, better thermal properties, easier wirebonding,
and lower weight.
The production of the space level hybrids can entail enhanced
screening steps beyond DDC’s standard flow. This includes
Condition A visual inspection, SEM analysis, and element eval-
uation for all integrated circuit die. For the hybrids, additional
screening includes Particle Impact Noise Detection (PIND), 320-
hour burn-in, 100% non-destructive wirebond pull, X-ray analy-
sis, as well as Destructive Physical Analysis (DPA) testing,
extended temperature cycling for QCI testing, and a moisture
content limit of 5000 PPM. TABLE 3 summarizes the procure-
ment screening, element evaluation, and hybrid screening used
in the production of the BU-65142.
MIL-H-38534
Element Evaluation:
Visual, Electrical, Wire
Bondability,24-Hour
Stabilization Bake,10
Temperature Cycles
5000 g’s constant acceleration
240-Hour Powered Burn-In
and 1000-Hour Life Test
(Burn-In and 1000-Hour Life
Test Are Only Required For
Active Components.)