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參數資料
| 型號： | BU-64703F8-202 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80 |
| 封裝： | CERAMIC, QFP-80 |
| 文件頁數： | 15/48頁 |
| 文件大?。?/td> | 405K |
| 代理商： | BU-64703F8-202 |
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22
Data Device Corporation
www.ddc-web.com
BU-64703
D-03/06-0
FIGURE 13. AUTO-CONFIGURATION - DMA READ TRANSFER TIMING
CLOCK IN
DTREQ
DTGRT
DTACK
MEMWR
MEMOE
D15-D0
MSTCLR
RTACTIVE
DATA VALID
t2
t3
t6
t5
t4
t7
t9
t11
t13
note1
t10
t8
t12
AUTO-CONFIGURATION - DMA SINGLE WORD READ
Note1: RTACTIVE asserted high 1 clock following DTACK high assuming self-test is not enabled.
When self-test is enabled RTACTIVE is delayed in the amount of 't12'.
See the table reference for details.
t1
(1)
During Auto-Configuration the SSRT Mark3 samples data three clock cycles following the falling edge of DTACK.
(2)
If self-test mode is not enabled, then RTACTIVE will go active high 1 clock cycle following the rising edge of DTACK. If self-test is enabled
then RTACTIVE will be delayed from going active high in accordance with ‘t12’.
t2
CLOCK IN rising to DTREQ low
ALL
ns
t3
DTREQ (low) - to - DTGRT delay time
ALL
s
t4
DTGRT low setup prior to CLOCK IN rising
ALL
ns
t6
CLOCK IN rising to DTACK low
ALL
ns
t7
DTGRT hold time following DTACK falling
ALL
ns
t9
Time for input data to become valid following falling edge of DTACK
t12
RTACTIVE high delayed from DTACK high (see Note 2)
t13
CLOCK IN rising to RTACTIVE high
ALL
ns
REF
DESCRIPTION
CLOCK
FREQUENCY
UNITS
TABLE FOR FIGURE 13. AUTO-CONFIGURATION - DMA READ TIMING
20 MHz
ns
16 MHz
ns
12 MHz
ns
10 MHz
ns
20 MHz
ms
16 MHz
ms
12 MHz
ms
10 MHz
ms
t5
DTGRT falling to DTACK low
20 MHz
ns
16 MHz
ns
12 MHz
ns
10 MHz
ns
t8
DTACK low pulse width
20 MHz
ns
16 MHz
ns
12 MHz
ns
10 MHz
ns
VALUE @3.3 VOLTS
MIN
TYP
MAX
40
10
40
30
40
120
157
220
270
1.6
2.0
2.7
3.2
105
118
138
155
185
200
215
235
250
265
318
333
348
385
400
415
t10
Data input hold time following sampling time (see Note 1)
ALL
ns
30
t11
CLOCK IN rising to DTREQ, DTACK, and MEMOE high
ALL
ns
40
t1
MSTCLR high delay to DTREQ low
20 MHz
ns
16 MHz
ns
12 MHz
ns
10 MHz
ns
35
50
65
47.5
62.5
77.5
68.3
83.3
98.3
85
100
115
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