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參數(shù)資料
| 型號： | BU-62864G3-490L |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 1 INCH, CERAMIC, QFP-72 |
| 文件頁數(shù)： | 29/99頁 |
| 文件大?。?/td> | 578K |
| 代理商： | BU-62864G3-490L |
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Data Device Corporation
62743_pre7_noSA-DB.DOC
www.ddc-web.com
8-07-02
35
NON-TEST REGISTER FUNCTION SUMMARY
A summary of the PCI Enhanced Mini-ACE’s 24 non-test registers follows.
Interrupt Mask Registers #1 and #2 are used to enable and disable interrupt
requests for various events and conditions.
Configuration Registers #1 and #2 are used to select the PCI Enhanced Mini-
ACE’s mode of operation, and for software control of RT Status Word bits, Active
Memory Area, BC Stop-On-Error, RT Memory Management mode selection, and
control of the Time Tag operation. Note that the LEVEL/PULSE* INTERRUPT
REQUEST bit in Configuration Register #2 MUST be set to 1 for correct PCI
operation.
Start/Reset Register is used for “command” type functions such as software
reset, BC/MT Start, Interrupt reset, Time Tag Reset, Time Tag Register Test,
Initiate RAM self-test, Clear self-test register, and Clear RT Halt. The Start/Reset
Register also includes provisions for stopping the BC in its auto-repeat mode,
either at the end of the current message or at the end of the current BC frame.
BC/RT Command Stack Register allows the host CPU to determine the pointer
location for the current or most recent message.
BC Instruction List Pointer Register may be read to determine the current
location of the Instruction List Pointer for the Enhanced BC mode.
BC Control Word/RT Subaddress Control Word Register:
In BC mode,
allows host access to the current word or most recent BC Control Word. The BC
Control Word contains bits that select the active bus and message format,
enable off-line self-test, masking of Status Word bits, enable retries and
interrupts, and specify MIL-STD-1553A or -1553B error handling. In RT mode,
this register allows host access to the current or most recent Subaddress Control
Word.
The Subaddress Control Word is used to select the memory
management scheme and enable interrupts for the current message.
Time Tag Register maintains the value of a real-time clock. The resolution of
this register is programmable from among 2, 4, 8, 16, 32, and 64
s/LSB. The
Start-of-Message (SOM) and End-of-Message (EOM) sequences in BC, RT, and
Message Monitor modes cause a write of the current value of the Time Tag
Register to the stack area of the RAM.
Interrupt Status Register #1 and #2 allow the host processor to determine the
cause of an interrupt request by means of one or two read accesses. The
interrupt events of the two Interrupt Status Registers are mapped to correspond
to the respective bit positions in the two Interrupt Mask Registers. Interrupt
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