
Data Device Corporation
62743_pre7_noSA-DB.DOC
www.ddc-web.com
8-07-02
3
Figure 1. PCI Enhanced Mini-ACE Block Diagram
TRANSCEIVER
A
CH. A
TRANSCEIVER
B
CH. B
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
RT ADDRESS
AND
ADDRESS LATCH
4K X 16
OR
64K X 17
SHARED
RAM
ADDRESS BUS
DATA BUS
MISCELLANEOUS
CLK_IN,
MSTCLR,SSFLAG/EXT_TRG
RTAD4-RTAD0, RTADP
TX/RX_A
TX/RX_B
TX_INH_A/B
RT-AD-LAT
INCMD/MCRST
TRANSMITTER
INHIBITS
33 MHZ,
32-BIT
PCI
SLAVE
INTERFACE
AD31-AD0
PAR
C/BE3#-C/BE#0
FRAME#, IRDY#,
IDSEL
TRDY#,STOP#,
DEVSEL#, PERR#, SERR#
(PCI) CLK
INT A#
PCI
Address/Data,
Parity,
and
Bus Command /
Byte Enable
PCI CONTROL
PCI CLK
PCI INTERRUPT
32 X 32
WRITE
FIFO