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    參數(shù)資料
    

    


    


    
型號(hào)：
BU-62864F3-110Q

    

    
廠(chǎng)商：
DATA DEVICE CORP

    

    
元件分類(lèi)：
微控制器/微處理器

    

    
英文描述：
2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72

    

    
封裝：
1 INCH, CERAMIC, QFP-72

    

    
文件頁(yè)數(shù)：
87/99頁(yè)

    

    
文件大小：
578K

    

    
代理商：
BU-62864F3-110Q


    

    

    

	
    
    
    

    
    
	
    Data Device Corporation
    62743_pre7_noSA-DB.DOC
    www.ddc-web.com
    8-07-02
    88
    Table 69. SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS
    RT ADDRESS
    SIGNAL
    NAME
    PIN
    (F & G
    Package)
    DESCRIPTION
    RTAD4
    (MSB) (I)
    8
    RTAD3 (I)
    6
    RTAD2 (I)
    4
    RTAD1 (I)
    3
    RTAD0
    (LSB) (I)
    1
    RT Address inputs. If bit 5 of Configuration Register #6, RT ADDRESS SOURCE, is programmed to
    logic “0” (default), then the PCI Enhanced Mini-ACE’s RT address is provided by means of these 5
    input signals. In addition, if RT ADDRESS SOURCE is logic “0”, the source of RT address parity is
    RTADP.
    There are many methods for using these input signals for designating the PCI Enhanced Mini-ACE’s
    RT address. For details, refer to the description of RT_AD_LAT.
    If RT ADDRESS SOURCE is programmed to logic “1”, then the PCI Enhanced Mini-ACE’s source for
    its RT address and parity is under software control, via data lines IfD5-D0. In this case, the RTAD4-
    RTAD0 and RTADP signals are not used.
    RTADP (I)
    10
    Remote Terminal Address Parity. This input signal must provide an odd parity sum with RTAD4-
    RTAD0 in order for the RT to respond to non-broadcast commands. That is, there must be an odd
    number of logic “1”s from among RTAD-4-RTAD0 and RTADP.
    RT_AD_LAT
    (I)
    11
    RT Address Latch.
    Input signal used to control the PCI PCI Enhanced Mini-ACE's internal RT
    address latch. If RT_AD_LAT is connected to logic “0”, then the PCI Enhanced Mini-ACE RT is
    configured to accept a hardwired (transparent) RT address from RTAD4-RTAD0 and RTADP.
    If RT_AD_LAT is initially logic “0”, and then transitions to logic “1”, the values presented on RTAD4-
    RTAD0 and RTADP will be latched internally on the rising edge of RT_AD_LAT.
    If RT_AD_LAT is connected to logic “1”, then the PCI Enhanced Mini-ACE’s RT address is latchable
    under host processor control. In this case, there are two possibilities: (1) If bit 5 of Configuration
    Register #6, RT ADDRESS SOURCE, is programmed to logic “0” (default), then the source of the RT
    Address is the RTAD4-RTAD0 and RTADP input signals; (2) If RT ADDRESS SOURCE is
    programmed to logic “1”, then the source of the RT Address is the lower 6 bits of the processor data
    bus, D5-D1 (for RTAD4-0) and D0 (for RTADP).
    In either of these two cases (with RT_AD_LAT = “1”), the processor will cause the RT address to be
    latched by: (1) writing bit 15 of Configuration Register #3, ENHANCED MODE, to logic “1”; (2) writing
    bit 3 of Configuration Register #4, LATCH RT ADDRESS WITH CONFIGURATION REGISTER #5,
    to logic “1”; and (3) writing to Configuration Register #5. In the case of RT ADDRESS SOURCE =
    “1”, then the values of RT address and RT address parity must be written to the lower 6 bits of
    Configuration Register #5, via D5-D0. In the case where RT ADDRESS SOURCE = “0”, the bit
    values presented on D5-D0 become “don’t care” .
    
    
    
    
    
    


    


    

    相關(guān)PDF資料
    		

    PDF描述
    		

    
    

    
BU-62864F3-142W
2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72

    

    
BU-62864F3-170Z
2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72

    

    
BU-62864F3-480Q
2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72

    

    
BU-62864F3-492Q
2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72

    

    
BU-62864F4-190S
2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72

    

    

    

    


    


    

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