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參數(shù)資料
| 型號： | BU-62864B3-152L |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128 |
| 封裝： | 0.815 X 0.815 INCH, 0.140 INCH HEIGHT, 1 MM PITCH, BGA-128 |
| 文件頁數(shù)： | 42/93頁 |
| 文件大?。?/td> | 504K |
| 代理商： | BU-62864B3-152L |
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Data Device Corporation
62743_pre2.DOC
www.ddc-web.com
8-15-01
47
response time requirement of 2 to 5
s, and multiple options for mode code
subaddresses, mode codes, RT status word, and RT BIT word.
The PCI Enhanced Mini-ACE RT protocol design implements all of the MIL-STD-
1553B message formats and dual redundant mode codes. The design has passed
validation testing for MIL-STD-1553B compliance. The PCI Enhanced Mini-ACE
RT performs comprehensive error checking, word and format validation, and
checks for various RT-to-RT transfer errors. One of the main features of the PCI
Enhanced Mini-ACE RT is its choice of memory management options. These
include single buffering by subaddress, double buffering for individual receive
subaddresses, circular buffering by individual subaddresses, and global circular
buffering for multiple (or all) subaddresses.
Other features of the PCI Enhanced Mini-ACE RT include a set of interrupt
conditions, an interrupt status queue with filtering based on valid and/or invalid
messages, internal command illegalization, programmable busy by subaddress,
multiple options on time tagging, and an “auto-boot” feature which allows the RT to
initialize as an online RT with the busy bit set following power turn-on.
RT MEMORY ORGANIZATION
TABLE 50
illustrates a typical memory map for an PCI Enhanced Mini-ACE RT with
4K RAM. The two Stack Pointers reside in fixed locations in the shared RAM
address space: address 0100 (hex) for the Area A Stack Pointer and address
0104 for the Area B Stack Pointer. In addition to the Stack Pointer, there are
several other areas of the shared RAM address space that are designated as fixed
locations (all shown in bold). These are for the Area A and Area B lookup tables,
the illegalization lookup table, the busy lookup table, and the mode code data
tables.
The RT lookup tables (reference TABLE 51) provide a mechanism for allocating
data blocks for individual transmit, receive, or broadcast subaddresses. The RT
lookup tables include subaddress control words as well as the individual data block
pointers. If command illegalization is used, address range 0300-03FF is used for
command illegalizing. The descriptor stack RAM area, as well as the individual
data blocks, may be located in any of the non-fixed areas in the shared RAM
address space.
Note that in TABLE 50, there is no area allocated for "Stack B". This is shown for
purpose of illustration. Also, note that in TABLE 50, the allocated area for the RT
command stacks is 256 words. However, larger stack sizes are possible. That is,
the RT command stack size may be programmed for 256 words (64 messages),
512, 1024, or 2048 words (512 messages) by means of bits 14 and 13 of
Configuration Register 3.
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