參數(shù)資料
型號(hào)： BU-62843G4-150W
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
封裝： 1 INCH, CERAMIC, QFP-72
文件頁(yè)數(shù)： 4/99頁(yè)
文件大?。?/td> 578K
代理商： BU-62843G4-150W
Data Device Corporation
62743_pre7_noSA-DB.DOC
www.ddc-web.com
8-07-02
12
The PACE acts as a target and responds to the following PCI commands:
Table 2.PCI Target Command Codes
Command type
Code (C/BE[3:0]#)
Memory Read
0110 (6h)
Memory Write
0111 (7h)
Configuration Read
1010 (Ah)
Configuration Write
1011 (Bh)
Memory Read Multiple
1100 (Ch)
Memory Read Line
1110 (Eh)
Memory Write and Invalidate
1111 (Fh)
The PACE does NOT implement the Memory Read Multiple, Memory Read Line
or Memory Write and Invalidate commands. However, in accordance with PCI
rules, the PACE will accept these requests and alias them to the basic memory
commands. For example, Memory Read Multiple and Memory Read Line
commands will be accepted and treated as Memory Read commands. Similarly,
the PACE will accept a memory Write and Invalidate command and treat it as a
Memory Write command.
ACE memory is accessed internally in 16-bit words, but memory is accessed
sequentially allowing for 32-bits of data to be read from the PCI bus. In other
words, if a 32-bit PCI read is requested the first 16 bits of data would be read
from the requested internal address, the next 16 bits of data would be read from
the initial internal address + 1, and then the resulting 32-bit double word would
be transferred to the PCI bus. The PCI Enhanced Mini-ACE supports 32-bit and
16-bit read and write operations, 8 bit reads will return 16 bit data, and 8 bit
writes are illegal and will cause target-aborts.
The ACE register mapping is located in PCI memory space. Although the PCI
Enhanced-MiniACE can be accessed in 32-bit words, all ACE registers are
accessed in 16 bit word reads / writes. If a 32-bit read is performed from the PCI
bus in ACE register space only the first 16 bits of data are valid.
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