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    參數(shù)資料
    型號(hào): BU-62843F4-400Q
    廠商: DATA DEVICE CORP
    元件分類: 微控制器/微處理器
    英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
    封裝: 1 INCH, CERAMIC, QFP-72
    文件頁數(shù): 89/99頁
    文件大?。?/td> 578K
    代理商: BU-62843F4-400Q
    Data Device Corporation
    62743_pre7_noSA-DB.DOC
    www.ddc-web.com
    8-07-02
    9
    Transformer must be a DDC recommended transformer or other
    transformer that provides an equivalent minimum CMRR.
    (8)
    Typical value for minimum intermessage gap time.
    Under software
    control, this may be lengthened to 65,535 ms - message time, in
    increments of 1
    s. If ENHANCED CPU ACCESS, bit 14 of Configuration
    Register #6, is set to logic “1”, then host accesses during BC Start-of-
    Message (SOM) and End-of-Message (EOM) transfer sequences could
    have the effect of lengthening the intermessage gap time. For each host
    access during an SOM or EOM sequence, the intermessage gap time will
    be lengthened by 6 clock cycles. Since there are 7 internal transfers
    during SOM, and 5 during EOM, this could theoretically lengthen the
    intermessage gap by up to 72 clock cycles; i.e., up to 7.2
    s with a 10
    MHz clock, 6.0
    s with a 12 MHz clock, 4.5 s with a 16 MHz clock, or 3.6
    s with a 20 MHz clock.
    (9)
    For Enhanced BC mode, the typical value for intermessage gap time is
    approximately 10 clock cycles longer than for the non-enhanced BC
    mode. That is, an addition of 1.0
    s at 10 MHz, 833 ns at 12 MHz, 625 ns
    at 16 MHz, or 500 ns at 20 MHz.
    (10) Software programmable (4 options).
    Includes RT-to-RT Timeout
    (measured mid-parity of transmit Command Word to mid-sync of
    transmitting RT Status Word).
    (11) Measured from mid-parity crossing of Command Word to mid-sync
    crossing of RT's Status Word.
    (12)
    0JC is measured to the bottom of the case
    (13) External 10
    F Tantalum and 0.1 F capacitors should be located as
    close as possible to Pins 20 and 72, and a 0.1
    F at pin 37. The BU-
    62864 should also have a 0.1
    F at pin 26.
    (14) MIL-STD-1760 requires that the PCI Enhanced Mini-ACE produce a 20
    Vp-p minimum output on the stub connection.
    (15) Power
    dissipation
    specifications
    assume
    a
    transformer
    configuration with external dissipation (while transmitting) of 0.14 watts for
    the active isolation transformer, 0.80 watts for the active bus coupling
    transformer, 0.45 watts for each of the two bus isolation resistors and 0.15
    watts for each of the two bus termination resistors.
    (16) The 5V tolerant pins are RTAD0-5, RTAD_PAR, RTAD_LAT, TXINH_A/B,
    and SSFLAG*/EXT_TRIG.
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