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參數(shù)資料
| 型號(hào)： | BU-62843F4-290Z |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 1 INCH, CERAMIC, QFP-72 |
| 文件頁數(shù)： | 30/99頁 |
| 文件大?。?/td> | 578K |
| 代理商： | BU-62843F4-290Z |
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Data Device Corporation
62743_pre7_noSA-DB.DOC
www.ddc-web.com
8-07-02
36
Status Register #2 contains an INTERRUPT CHAIN bit, used to indicate an
interrupt event from Interrupt Status Register #1.
Configuration Registers #3, #4, and #5 are used to enable many of the PCI
Enhanced Mini-ACE’s advanced features that were implemented by the prior
generation products, the ACE and Mini-ACE (Plus). For BC, RT, and MT modes,
use of the ENHANCED MODE enables the various read-only bits in
Configuration Register #1. For BC mode, ENHANCED mode features include
the expanded BC Control Word and BC Block Status Word, additional Stop-On-
Error and Stop-On-Status Set functions, frame auto-repeat, programmable
intermessage gap times, automatic retires, expanded Status Word Masking, and
the capability to generate interrupts following the completion of any selected
message. For RT mode, the enhanced mode features include the expanded RT
Block Status Word, combined RT/Selective Message Monitor mode, internal
wrapping of the RTFAIL* output signal to the RTFLAG* RT Status Word bit; and
the alternate (fully software programmable) RT Status Word. For MT mode, use
of the enhanced mode enables the Selective Message Monitor, the combined
RT/Selective Monitor modes, and the monitor triggering capability.
RT/Monitor Data Stack Address Register provides a read/writable indication of
the last data word stored for RT or Monitor modes.
BC Frame Time Remaining Register provides a read-only indication of the time
remaining in the current BC frame. In the enhanced BC mode, this timer may be
used for minor or major frame control, or as a watchdog timer for the BC
message sequence control processor. The resolution of this register is 100
s/LSB.
BC Time Remaining to Next Message Register provides a read-only indication
of the time remaining before the start of the next message in a BC frame. In the
enhanced BC mode, this timer may be also be used for the BC message
sequence control processor’s Delay (DLY) instruction, or for minor or major
frame control. The resolution of this register is 1
s/LSB.
BC Frame Time/RT Last Command/MT Trigger Word Register. In BC mode,
this register is used to program the BC frame time, for use in the frame auto-
repeat mode. The resolution of this register is 100
s/LSB, with a range up to
6.55 seconds. In RT mode, this register stores the current (or most previous)
1553 Command Word processed by the PCI Enhanced Mini-ACE RT. In the
Word Monitor mode, this register is used to specify a 16-bit Trigger (Command)
Word.
The Trigger Word may be used to start or stop the monitor, or to
generate interrupts.
BC Initial Instruction List Pointer Register enables the host to assign the
starting address for the enhanced BC Instruction List.
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