
Data Device Corporation
62743_pre7_noSA-DB.DOC
www.ddc-web.com
8-07-02
23
Table 18. ACE Register Address Mapping
INTERNAL
ADDRESS
LINES
A4 A3 A2 A1 A0
PCI
BAR1
ADDR
OFFSET
REGISTER
DESCRIPTION/ACCESIBILITY
0
00h
Interrupt Mask Register #1 (RD/WR)
0
1
04h
Configuration Register #1 (RD/WR)
0
1
0
08h
Configuration Register #2 (RD/WR)
0
1
0Ch
Start/Reset Register (WR)
0
1
0Ch
Non-Enhanced BC or RT Command Stack Pointer/Enhanced BC
Instruction List Pointer Register (RD)
0
1
0
10h
BC Control Word/
RT Subaddress Control Word Register (RD/WR)
0
1
0
1
14h
Time Tag Register (RD/WR)
0
1
0
18h
Interrupt Status Register #1(RD)
0
1
1Ch
Configuration Register #3 (RD/WR)
0
1
0
20h
Configuration Register #4 (RD/WR)
0
1
0
1
24h
Configuration Register #5 (RD/WR)
0
1
0
1
0
28h
RT/Monitor Data Stack Address Register (RD/WR)
0
1
0
1
2Ch
BC Frame Time Remaining Register (RD)
0
1
0
30h
BC Time Remaining to Next Message Register (RD)
0
1
0
1
34h
Non-Enhanced BC Frame Time/Enhanced BC Initial Instruction
Pointer /RT Last Command/MT Trigger Word Register (RD/WR)
0
1
0
38h
RT Status Word Register (RD)
0
1
3Ch
RT BIT Word Register (RD)
1
0
40h
Test Mode Register 0
1
0
1
44h
Test Mode Register 1
1
0
1
0
48h
Test Mode Register 2
1
0
1
4Ch
Test Mode Register 3
1
0
1
0
50h
Test Mode Register 4
1
0
1
0
1
54h
Test Mode Register 5
1
0
1
0
58h
Test Mode Register 6
1
0
1
5Ch
Test Mode Register 7
1
0
60h
Configuration Register #6 (RD/WR)
1
0
1
64h
Configuration Register #7 (RD/WR)
1
0
1
0
68h
RESERVED
1
0
1
6Ch
BC Condition Code Register (RD)
1
0
1
6Ch
BC General Purpose Flag Register (WR)
1
0
70h
BIT Test Status Register (RD)
1
0
1
74h
Interrupt Mask Register #2 (RD/WR)
1
0
78h
Interrupt Status Register #2 (RD)
1
7Ch
BC General Purpose Queue Pointer/
RT-MT Interrupt Status Queue Pointer Register (RD/WR)